User guide

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SystemVerilog Testbench Constructs
Note:
You can specify only one default clocking block in a program,
module, or interface. VCS issues a compilation error if you specify
more than one default clocking block.
For example:
program test( input bit clk, input reg [15:0] data );
default clocking bus @(posedge clk);
input data;
endclocking
initial begin
## 5;
if ( bus.data == 10 )
## 1;
else
##2;
end
endprogram
Cycle Delays
Cycle delays can be used to postpone or delay the execution by a
specified number of clock cycles or clocking events. The term cycle
refers to the clock associated with the default clocking block.The ##
operator is used to specify cycle delay.
Syntax:
## integral_number | integer | (expression)
expression