User guide

24-195
SystemVerilog Testbench Constructs
endclocking
Clocking blocks that use the same clock can share the same
synchronization event. For example:
program test( input bit clk_1, input reg [15:0] address,
input reg [15:0] data );
default clocking data @(posedge clk_1);
input data;
endclocking
clocking address @(posedge clk_1);
input address;
endclocking
Clocking Block Scope and Lifetime
Signals associated with a clocking block can be accessed by using
a dot (.) operator. For example:
clocking CB_1 @(posedge clk_1);
input data;
input address;
endclocking
CB_1.data;
CB_1.address;
The scope of a clocking block is local to its enclosing module,
interface, or program. Clocking blocks cannot be nested. They cannot
be declared inside packages, functions, tasks, and outside all
declarations in a compilation unit. The lifetime of a clocking block is
static.