User guide

24-194
SystemVerilog Testbench Constructs
Hierarchical Expressions
Every signal in a clocking block is associated with a program port or
a cross module reference.
As described when defining hierarchical_identifier, the hierarchical
path is assigned to the defined in the clocking block.
clocking cb2 @ (negedge clk);
input #0 b = top.q;
endclocking
Below is an example of the hierarchical_identifier as a program port:
program p1(output reg out3,input logic clk,input reg in );
clocking cb @(posedge clk);
output #3 out2 = out3;//out3 and in = program ports
input #0 out1 = in;
endclocking
endprogram
Signals in Multiple Clocking Blocks
The signals (clocks, input, outputs, or inouts) associated with one
clocking block can be associated with any other clocking blocks. For
example:
program test( input bit clk_1, input bit clk_2,
input reg [15:0] data );
default clocking data @(posedge clk_1);
input data;
endclocking
clocking address @(posedge clk_2);
input data;