User guide

3-8
Compiling and Elaborating Your Design
Initializing Memories and Regs
VCS has compile-time options for initializing all bits of memories and
regs to the 0, 1, X, or Z value. These options are:
+vcs+initmem+0|1|x|z
Initializes all bits of all memories in the design.
+vcs+initreg+0|1|x|z
Initializes all bits of all regs in the design.
Note:
+vcs+initmem+, and +vcs+initreg+ options work only for
Verilog portion of the design.
The +vcs+initmem option initializes regular memories and
multi-dimensional arrays of the reg data type. For example:
reg [7:0] mem [7:0][15:0];
The +vcs+initmem option does not initialize multi-dimensional
arrays of any other data type.
The +vcs+initreg option does not initialize registers (variables)
other than the reg data type.
To prevent race conditions, avoid the following when you use these
options:
• Assigning initial values to a regs in their declaration when the
value you assign is not the same as the value specified with the
+vcs+initreg option.
For example:
reg [7:0] r1 8’b01010101;