User guide

24-192
SystemVerilog Testbench Constructs
reg out3;
reg out1;
reg clk = 0;
p1 p(out3,clk,out1);
assign out1 = out3;
initial forever begin
clk = 0;
#10;
clk = 1;
#10;
end
endmodule
program p1(output reg out3,input logic clk,input reg in );
clocking cb @(posedge clk);
output #3 out2 = out3; //CB output signal
input #0 out1 = in;
endclocking
initial
#200 $finish;
initial begin
$display($time,,,cb.out1);
cb.out2 <= 0; //driving output at "0" time
@(cb.out1); //sampling input for change
$display($time,,,cb.out1);
#100;
$display($time,,,cb.out1);
cb.out2 <= 1; //driving o/p at posedge of clk
@(cb.out1);
$display($time,,,cb.out1);