User guide

24-191
SystemVerilog Testbench Constructs
input #1 i1;
where i1 is the signal_identifier.
Note:
A clocking block signal can only be connected to a scalar, vector,
packed array, integer or real variable. Program signals are not
allowed in clocking block signal declarations.
hierarchical_identifier
Hierarchical path to the signal being assigned to the
signal_identifier. For example:
input negedge #2 i = top.i2;
where i2 is defined in a module top.
Note:
see page 182 of the System Verilog LRM 3.1a for a formal
definition of the syntax for declaring the clocking block.
Note:
Slices and concatenations are not yet implemented
A single skew can be declared for the entire clocking block. For
example:
default input #10;
You can override default skews when you declare a signal.
The following example includes a clocking block embedded in a
program:
`timescale 1ns/1ns
module top;