User guide

24-190
SystemVerilog Testbench Constructs
clocking_skew
Determines how long before the synchronized edge the signal is
sampled, or how long after the synchronized edge the signal is
driven. A clocking_skew can consist of an edge identifier and a
delay control, just an edge identifier, or just the delay control. The
edge identifiers are posedge and negedge. The edge can be
specified only if the clocking event is a singular clock (that is, a
simple edge of a single signal like @(posedge clk), @(clk),
@(negedge top.clk), etc.).The delay control is introduced by "#"
followed by the delay value. The following are examples of legal
clocking_skews:
input #0 i1;
output negedge #2 i2;
input #1 output #2;
Note:
Time literals (e.g., #10ns and #2ns) are not supported in this
release.
The skew for an input signal is implicitly negative (that is, sampling
occurs before the clock event). The skew for an output signal is
implicitly positive (that is, the signal is driven after the clock event).
Note:
#1step is the default input skew unless otherwise specified.
However, an explicit #1step skew is not yet supported.
signal_identifier
Identifies a signal in the scope enclosing the clocking block
declaration, and declares the name of a signal in the clocking
block. Unless a hierarchical_expression is used, both the signal
and the clocking_item names shall be the same. For example: