User guide

24-189
SystemVerilog Testbench Constructs
clocking_identifier
Name of the clocking block being declared.
clocking_event
Event that acts as the clock for the clocking block (for example:
posedge, negedge of a clocking signal):
@(posedge clk)
or
@(clk)
Note:
Program signals cannot be used inside a clocking event
expression.
clocking_dir
Direction of the signal: input, output or inout. If you specify more
than one clocking_dir, they must be in the order input...output:
input clocking_skew output clocking_skew
The inout signal cannot be used in the declaration of a default
skew. Also, if the clocking_dir of a clocking block signal is inout,
you cannot specify a clocking_skew. For example:
inout #1 d; //results in a syntax error
inout d; //is fine