User guide

24-188
SystemVerilog Testbench Constructs
evt1 === evt2
evt1 != evt3
evt3 != null
In comparing named events, the case equality operator === works
the same as the equality operator ==, and the case inequality operator
!== works the same as the inequality operator !=.
Clocking Blocks
A clocking block encapsulates a group of signals that are sampled or
synchronized by a common clock. It defines the timing behavior of
those signals with respect to the associated clock. Consequently,
timing and synchronization details for these signals is separate from
the structural, functional, and procedural elements of the testbench.
This enables synchronous events, input sampling, and synchronous
drives to be written without explicitly using clocks or specifying timing.
Clocking blocks can be declared inside a program block or inside an
interface.
Clocking Block Declaration
The syntax for declaring a clocking block is:
clocking clocking_identifier @clocking_event;
[default clocking_dir clocking_skew [clocking_dir
clocking_skew];]
{clocking_dir [clocking_skew][clocking_dir
[clocking_skew]]signal_identifier [=
hierarchical_identifier]
{,signal_identifier [= hierarchical_identfier]};}
endclocking[: clocking_identifier]