User guide

24-153
SystemVerilog Testbench Constructs
// Begin file input.vr
program top;
foo f;
f = new();
f.myTask();
endprogram
class foo;
int i;
task myTask();
$display("Executing original code\n");
endtask
endclass
extends aoe1 (foo) dominates(aoe2);
around task myTask();
proceed;
$display("around in aoe1\n");
endtask
endextends
extends aoe2 (foo);
around task myTask();
proceed;
$display("around in aoe2\n");
endtask
endextends
// End file input.sv
When aoe1 dominates aoe2, as in func1, the output when the
program is executed is:
Executing original code
around in aoe2
around in aoe1
Example 24-16
// Begin file input.vr
program top;
foo f;