User guide

24-145
SystemVerilog Testbench Constructs
since aspect_3 is coded later in Input.vr than aspect_2, aspect_3
has higher precedence than aspect_2. Therefore, the precedence of
these aspect extensions in the decreasing order of precedence is:
{aspect_1, aspect_3, aspect_2}
This implies that the advice(s) within aspect_2 have lower
precedence than advice(s) within aspect_3, and advice(s) within
aspect_3 have lower precedence than advice(s) within aspect_1.
Therefore, advice 2 has lower precedence than advice 3 and advice
4. Both advice 3 and advice 4 have lower precedence than advice 1.
Between advice 3 and advice 4, advice 4 has higher precedence as
it is defined later than advice 3. That puts the order of advices in the
increasing order of precedence as:
{2, 3, 4, 1}.
Adding of Introductions
Target scope refers to the scope of the class definition that is being
extended by an aspect. Introductions in an aspect are appended as
new members at the end of its target scope. If an extension A has
precedence over extension B, the symbols introduced by A are
appended first.
Within an aspect extension, symbols introduced by the extension are
appended to the target scope in the order they appear in the
extension.
There are certain rules according to which an introduction symbol
with the same identifier name as a symbol that is visible in the target
scope, may or may not be allowed as an introduction. These rules
are discussed later in the chapter.