User guide

24-144
SystemVerilog Testbench Constructs
class packet;
...
// Other member fields/methods
...
task send();
$display("Sending data\n");
endtask
endclass
extends aspect_1(packet) dominates (aspect_2, aspect_3);
after task send(); // Advice 1
$display("Aspect_1: send advice after\n");
endtask
endextends
extends aspect_2(packet);
after task send() ; // Advice 2
$display("Aspect_2: send advice after\n");
endtask
endextends
extends aspect_3(packet);
around task send(); // Advice 3
$display("Aspect_3: Begin send advice around\n");
proceed;
$display("Aspect_3: End send advice around\n");
endtask
before task send(); // Advice 4
$display("Aspect_3: send advice before\n");
endtask
endextends
// End of file Input.vr
In Example 24-11, multiple aspect extensions for a class named
packet are defined in a single SV file. As specified in the dominating
list of aspect_1, aspect_1 dominates both aspect_2 and aspect_3.
As per the dominating lists of the aspect extensions, there is no
precedence order established between aspect_2 and aspect_3, and