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24-134
SystemVerilog Testbench Constructs
stmt ::= statement
| proceed ;
hide_list ::=
hide([hide_item {,hide_item}]);
hide_item ::=
// Empty
| virtuals
| rules
The symbols in boldface are keywords and their syntax are as
follows:
extends_identifier
Name of the aspect extension.
class_identifier
Name of the class that is being extended by the extends directive.
dominate_list
Specifies extensions that are dominated by the current directive.
Domination defines the precedence between code woven by
multiple extensions into the same scope. One extension can
dominate one or more of the other extensions. In such a case, you
must use a comma-separated list of extends identifiers.
dominates(extends_identifier
{,extends_identifier});
A dominated extension is assigned lower precedence than an
extension that dominates it. Precedence among aspects extensions
of a class determines the order in which introductions defined in the