User guide

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SystemVerilog Testbench Constructs
Syntax:
extends_directive ::=
extends extends_identifier
(class_identifier)[dominate_list];
extends_item_list
endextends
dominate_list ::=
dominates(extends_identifier
{,extends_identifier});
extends_item_list ::=
extends_item {extends_item}
extends_item ::=
class_item
| advice
| hide_list
class_item ::=
class_property
| class_method
| class_constraint
| class_coverage
| enum_defn
advice ::= placement procedure
placement ::=
before
| after
| around
procedure ::=
| optional_method_specifiers task
task_identifier(list_of_task_proto_formals);
| optional_method_specifiers function
function_type
function_identifier(list_of_function_proto_formals)
endfunction
advice_code ::= [stmt] {stmt}