User guide

24-126
SystemVerilog Testbench Constructs
repeat Loops
The repeat loop is used to loop over a production a specified number
of times.
The syntax to declare a repeat loop within a production definition is:
repeat(express) production_item
expression
Can be any valid SystemVerilog expression that evaluates to a
non-negative integer, including functions that return a numeric
value.
The expression is evaluated when the production definition is
executed. The value specifies how many times the corresponding
production item is executed. The following is an example of a
production definition using a repeat loop.
randsequence()
...
seq_block : repeat (random() ) integer_instruction;
...
endsequence
This example defines the production seq_block, which repeats the
production item integer_instruction a random number of
times, depending on the value returned by the random() system
function.
break Statement
The break statement is used to terminate a randsequence block.