User guide

24-125
SystemVerilog Testbench Constructs
case Statements
A general selection mechanism is provided by the case statement.
The syntax to declare a case statement within a production definition
is:
case(expression)
rs_case_item {rs_case_item}
endcase
expression
Is evaluated. The value of the expression is successively
checked, in the order listed, against each rs_case_item. The
production corresponding to the first matching case found is
executed, and control is passed to the production definition
whose name is in the case item with the matching case
expression. If other matches exist, they are not executed. If no
case item value matches the evaluated primary expression and
there is no default case, nothing happens.
rs_case_item
Can be any valid SystemVerilog expression or
comma-separated list of expressions. Expressions separated by
commas allow multiple expressions to share the same statement
block. The syntax is:
expression{,expression}: production_item | default [:]
production_item;
A case statement must have at least one case item aside from the
default case, which is optional. The default case must be the last
item in a case statement. The following is an example of a production
definition using a case statement: