User guide

24-123
SystemVerilog Testbench Constructs
weight_specification
The syntax for weight_specification is:
integral_number | ps_identifier | (expression)
The expression can be any valid SystemVerilog expression that
returns a non-negative integer. Function calls can be made within
the expression, but the expression must return a numeric value,
or else a simulation error is generated.
Assigning weights to a production item affects the probability that it
is selected when the randsequence block is called. Weight should
only be assigned when a selection is forced with the | operator. The
weight for each production item is evaluated when its production
definition is executed. This allows you to change the weights
dynamically throughout a sequence of calls to the same production.
if-else Statements
A production can be conditionally referenced using an if-else
statement.
The syntax to declare an if-else statement within a production
definition is:
if(expression) product_item [else production_item]
expression
Can be any valid SystemVerilog expression that evaluates to a
boolean value.