User guide

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SystemVerilog Testbench Constructs
SystemVerilog’s sequence generation allows you to specify the
syntax of valid sequences using BNF-like notation. Random
sequences are ideal for generating streams of instructions for which
it is easier to specify the syntax of valid streams than the constraints
on specific values.
This section includes the following:
•RSG Overview
• Production Declaration
• Production Controls
RSG Overview
The syntax for programming languages is often expressed in Backus
Naur Form (BNF) or some derivative thereof. Parser generators use
this BNF to define the language to be parsed. However, it is possible
to reverse the process. Instead of using the BNF to check that
existing code fits the correct syntax, the BNF can be used to
assemble code fragments into syntactically correct code. The result
is the generation of pseudo-random sequences of text, ranging from
sequences of characters to syntactically and semantically correct
assembly language programs.
SystemVerilog’s implementation of a stream generator, the RSG, is
defined by a set of rules and productions encapsulated in a
randsequence block.
The general syntax to define a RSG code block is:
randsequence ([production_identifier])
production {production}
endsequence