User guide

24-116
SystemVerilog Testbench Constructs
d3 = a.x;
a.srandom(r);
d1 = a.randomize();
if(d1 == 1)
d4 = a.x;
if((d2 == d4) && (d2 != d3))
$display("test passed");
else
$display("test failed");
end
endprogram
Output of the above program is:
test passed
randcase Statements
The randcase construct specifies a block of statements with
corresponding weights attached to them. Weights can be any
expression. When a randcase statement occurs, one of the statement
with weights is executed at random. If the weight is an expression,
then it is evaluated each time the randcase statement is executed. If
the weight is zero, then that branch is not executed. The randcase
statements can be nested.
program test;
int a= 2;
logic [3:0] b;
//variables to keep count of how many time a particular case
//is executed in randcase
int count_2,count_c;
function f1();