User guide

24-111
SystemVerilog Testbench Constructs
Random Number Generation
SystemVerilog includes a number of system functions to work with
random numbers. Some of these are:
$urandom()
The system function $urandom() generates pseudorandom numbers.
It returns an unsigned 32-bit number every time this function is called.
The syntax is:
$urandom( seed )
The seed is an optional argument that determines the sequence of
the random number that are generated. It could also be an
expression. The same sequence is always generated for the same
seed.
The following program explains the usage of $urandom().
program test();
bit [7:0] a,b,c,d;
initial begin
$display("Generation of random number with seed 3 :");
a = $urandom(3);
b = $urandom();
c = $urandom();
d = $urandom();
$display("a = %0d,b= %0d, c = %0d, d = %0d",a,b,c,d);
$display("Generation of random number with seed 4 :");
a = $urandom(4);
b = $urandom();
c = $urandom();
d = $urandom();
$display("a = %0d,b= %0d, c = %0d, d = %0d",a,b,c,d);