User guide

24-107
SystemVerilog Testbench Constructs
generateRandomAddresses(`N);
// turn OFF "data" random variable in "bb"
bb.data.rand_mode(0);
$display("======one random variable ON ======");
generateRandomAddresses(`N);
// turn OFF all random variables in "bb"
bb.rand_mode(0);
$display("======both random variables OFF======");
generateRandomAddresses(`N);
// turn ON "data" constraint in "bb"
bb.data.rand_mode(1);
$display("======one random variable ON========");
generateRandomAddresses(`N);
// turn ON all random variable in "bb"
bb.rand_mode(1);
$display("======both random variables ON ======");
generateRandomAddresses(`N);
end
endprogram
Output of the above program:
======both random variables ON =======
bb.addr = 88,, bb.data = 12
bb.addr = 49,, bb.data = 381
bb.addr = 185,, bb.data = 5
bb.addr = 212,, bb.data = 486
bb.addr = 49,, bb.data = 219
=======one random variable ON ========
bb.addr = 3,, bb.data = 219
bb.addr = 130,, bb.data = 219
bb.addr = 26,, bb.data = 219
bb.addr = 90,, bb.data = 219
bb.addr = 121,, bb.data = 219
======both random variables OFF=======
bb.addr = 121,, bb.data = 219