User guide

24-106
SystemVerilog Testbench Constructs
function int object.randvar_identifier::rand_mode();
rand_mode() returns -1 if the specified variable does not exist within
the class hierarchy or it exists but is not declared as rand or randc.
In the following example, there are two random variables defined in
a class, bus. The rand_mode() method, when used as a task, turns
on and off the random variables, addr and data. rand_mode() is
also being used as a function to report on the value (ON or OFF) of
the two random variables.
`define N 5
program test;
class bus;
rand bit [15:0] addr;
rand bit [31:0] data;
constraint CC { data > 0; addr > 0; addr < 255; data
< 512;}
endclass
task generateRandomAddresses(integer how_many);
integer i;
for(i = 1; i <= how_many; i++) begin
bb.randomize();
$display("bb.addr = %d,, bb.data =
%d",bb.addr,bb.data);
end
endtask
bus bb = new;
initial begin
// By default all random variables are ON
if (bb.addr.rand_mode() && bb.data.rand_mode())
begin
$display("======both random variables ON
======");
end
else
$display("Error with rand_mode");