User guide

24-105
SystemVerilog Testbench Constructs
bb.addr = 36593
bb.addr = 19491
bb.addr = 6853
bb.addr = 48017
=========one constraint ON =======
bb.addr = 11
bb.addr = 8
bb.addr = 15
bb.addr = 7
bb.addr = 4
=========both constraints ON =======
bb.addr = 2
bb.addr = 10
bb.addr = 12
bb.addr = 10
bb.addr = 8
Disabling Random Variables
SystemVerilog provides the predefined rand_mode() method to
control whether a random variable is active or inactive. Initially, all
random variables are active.
The rand_mode() method can be used either as a task or a function.
The rand_mode() task specifies whether or not the random variable
is ON or OFF.
task object[.randvar_identifier]::rand_mode(bit ON |
OFF);
where ON is “1” and OFF is “0.”
As a function, rand_mode() reports the current value (ON or OFF) of
the specified variable.
Syntax: