User guide

24-99
SystemVerilog Testbench Constructs
However, when unidirectional constraints are used in the presence
of randc variables, it is possible that rand variables could be solved
before randc variables.
Example 24-8
randc bit[3:0]x;
rand bit[3:0] y,z;
constraint b1{
y inside {0,1};
x<12;
if($void(y)){
x<5;
} else{
x<10;
}
z>x;
}
The sequence in which the constraints are solved is:
1. y is solved using the constraint y inside {0,1}.
2. x is solved using the constraints if(y) x<5 else x<10;
x<12.
3. z is solved using the constraint z>x.
Static Constraint Blocks
The keyword static preceding the keyword constraint, makes a
constraint block static, and calls to the constraint_mode()
method occur to all instances of the constraint in all instances of the
constraint’s class.
static constraint c1 { data1 < data2;}