User guide

24-98
SystemVerilog Testbench Constructs
1. y is solved using the constraint y inside {0,1}.
2. z, x are solved using the default constraint x<=y and the
non-default constraints z==y; z=>x ==0;. the default
constraint applies if and only if z is 0 (that is, if and only if y was
chosen as 0 in the previous partition.).
Semantics of randc
There is an existing semantic of the solver, wherein randc variables
are solved in partitions that contain a single randc variable, after
which they behave like state variables when solving for non-randc
rand variables.
Example 24-7
randc bit[3:0]x;
rand bit[3:0] y,z;
constraint b1{
y inside {0,1};
x<12;
if(y){
x<5;
} else{
x<10;
}
z>x;
}
The sequence in which the above constraints are solved is:
1. x is solved for using the constraint x<12.
2. y and z are solved for using the remaining constraints. Note that
this could result in a failure, depending on the solution picked in
the previous step. For example, if x were picked as 11 in the
previous step, then there would be no solution for y in this step.
Thus, all randc variables are solved before all rand variables.