User guide

24-87
SystemVerilog Testbench Constructs
Output
First call to randomize, rand mode of x and y are ON
x = 3 y = 7
Second call to randomize, rand mode of x and y are OFF
x = 0 y = 0
Return status of randomize is 1
In the first call to randomize, the default is not overridden and
consequently, x + y == 10;
In the second call to randomize, the rand mode of x and y are turned
OFF and both are set to 0. In this call the default variables are rand
mode OFF and the default constraint is there fore ignored. If not the
randomize() would fail and return 0.
Variable Ordering
In an implication like the following:
constraint c1 { select -> data == 0;}
The select variable “implies” that data is 0, in this case, when select
is 1, data is 0.
The default behavior is for the constraint solver to solve for both
select and data at the same time. Sometimes you can assist the
constraint solver by telling it to solve for one variable first. You can
do this with another constraint block that specifies the order in which
the constraint solver solves the variables:
constraint c1 { select -> data == 0;}
constraint c2 ( solve select before data;}
Note:
Ordering also changes the distribution of values.