User guide

24-85
SystemVerilog Testbench Constructs
Output
x = 10 y = 0
In the example, x = 10 since only the second constraint in the default
constraint block is overridden.
program test;
class A;
rand reg[3:0] x;
rand reg[3:0] y;
rand reg g;
default constraint T{x + y == 10;}
constraint E {g -> y == 1;}
function void post_randomize();
$display("x = %0d y = %0d g = %0d\n", x, y, g);
endfunction
endclass
initial
begin
integer ret;
A a = new;
$display("First call to randomize,
the guard g evaluates to FALSE\n");
ret = a.randomize() with {a.g == 0;};
$display("Second call to randomize, the
guard g evaluates to TRUE\n");
ret = a.randomize() with {a.g == 1;};
$display("Third call to randomize, constraint mode of
constraint block E is OFF \n");
a.E.constraint_mode(0);
a.g.rand_mode(0);
ret = a.randomize();
end
endprogram