User guide

24-80
SystemVerilog Testbench Constructs
program prog;
class myclass;
rand bit [7:0] randvar;
endclass
class myextclass extends myclass;
rand myclass left = new;
rand myclass right = new;
constraint c1 {left.randvar <= randvar;
right.randvar <= randvar;}
endclass
endprogram
In this example, class myextclass extends class myclass. In class
myextclass are two randomized objects (or instances) of class
myclass. They are named left and right and are randomized because
they are declared with the rand keyword.
Constraint C1 specifies that the version of randvar in the left object
must be less than or equal to randvar in myclass. Similarly the version
of randvar in the right object must be less than or equal to randvar in
myclass.
Constraint c1 is a global constraint because it refers to a variable in
myclass.
Default Constraints
You can specify default constraints by placing the keyword “default”
ahead of a constraint block definition, as illustrated in the following
example:.
[default] constraint constraint_name {constraint_expressions}