User guide

24-79
SystemVerilog Testbench Constructs
$display("randcvar = %0d norandvar = %0b at %0t",
bus.randcvar, bus.norandvar,$time);
endprogram
constraint c1 { if (norandvar == 1)
randcvar == 0;
else
randcvar inside {[1:3]};}
Constraint c1 specifies that when variable norandvar has the 1 value,
VCS constrains random-cyclic variable randcvar to 0, and when
norandvar doesn’t have the 1 value, in other words when it has the
0 value, VCS constrains random-cyclic variable randcvar to 1, 2, or 3.
The $display system task displays the following:
randcvar = 1 norandvar = 0 at 1
randcvar = 2 norandvar = 0 at 2
randcvar = 3 norandvar = 0 at 3
randcvar = 3 norandvar = 0 at 4
randcvar = 0 norandvar = 1 at 5
randcvar = 0 norandvar = 1 at 6
randcvar = 0 norandvar = 1 at 7
randcvar = 0 norandvar = 1 at 8
randcvar = 0 norandvar = 1 at 9
randcvar = 1 norandvar = 0 at 10
randcvar = 2 norandvar = 0 at 11
randcvar = 3 norandvar = 0 at 12
randcvar = 3 norandvar = 0 at 13
randcvar = 2 norandvar = 0 at 14
When norandvar is 1, VCS always assigns 0 to randcvar.
Global Constraints
Constraint expressions involving random variables from other objects
are called global constraints.