User guide

24-78
SystemVerilog Testbench Constructs
randcvar = 0 norandvar = 0 at 13
randcvar = 1 norandvar = 0 at 14
When variable norandvar is 0, random-cyclic variable randcvar is
either 0 or 1. When variable norandvar is 1, random-cyclic variable
randcvar is always 0.
if else Constraints
An alternative to an implication constraint is the if else constraint.
The if else constraint allows a constraint or constraint set on the
else condition.
program prog;
class Bus;
randc bit [2:0] randcvar;
bit norandvar;
constraint c1 { if (norandvar == 1)
randcvar == 0;
else
randcvar inside {[1:3]};}
endclass
Bus bus = new;
initial
begin
bus.norandvar = 0;
#5 bus.norandvar = 1;
#5 bus.norandvar = 0;
#5 $finish;
end
initial
repeat (15)
#1 if (bus.randomize() ==1)