User guide

24-77
SystemVerilog Testbench Constructs
constraint c1 { (norandvar == 1) -> (randcvar ==
0);}
endclass
Bus bus = new;
initial
begin
bus.norandvar = 0;
#5 bus.norandvar = 1;
#5 bus.norandvar = 0;
#5 $finish;
end
initial
repeat (15)
#1 if (bus.randomize() ==1)
$display("randcvar = %0b norandvar = %0b at %0t",
bus.randcvar, bus.norandvar,$time);
endprogram
In constraint c1, when variable norandvar has a 1 value (the
implication expression), VCS constrains random variable randcvar to
0. The -> token is the implication operator.
The $display system task displays the following:
randcvar = 0 norandvar = 0 at 1
randcvar = 1 norandvar = 0 at 2
randcvar = 0 norandvar = 0 at 3
randcvar = 1 norandvar = 0 at 4
randcvar = 0 norandvar = 1 at 5
randcvar = 0 norandvar = 1 at 6
randcvar = 0 norandvar = 1 at 7
randcvar = 0 norandvar = 1 at 8
randcvar = 0 norandvar = 1 at 9
randcvar = 1 norandvar = 0 at 10
randcvar = 0 norandvar = 0 at 11
randcvar = 0 norandvar = 0 at 12