User guide

24-72
SystemVerilog Testbench Constructs
External Declaration
You can declare a constraint block outside of a class declaration.
program prog1;
class cl1;
rand integer rint1, rint2, rint3;
constraint constr1;
endclass
constraint cl1::constr1 { rint1 < rint2; rint2 < rint3; }
endprogram
Inheritance
Constraints follow the same rules of inheritance as class variables,
tasks, and functions.
class myclass;
rand logic [1:0] log1,log2,log3;
randc logic [1:0] log4;
constraint c1 {log1 > 0;}
constraint c2 {log2 < 3;}
endclass
class myclass2 extends myclass;
constraint c2 {log2 < 2;}
endclass
myclass2 mc = new;
The keyword extends specifies that class myclass2 inherits from
class myclass and then can change constraint c2, specifying that it
must be less than 2, instead of less than 3.