User guide

24-70
SystemVerilog Testbench Constructs
class myclass;
rand logic [1:0] log1,log2,log3;
randc logic [1:0] log4;
constraint c1 {log1 > 0;}
constraint c2 {log2 < 3;}
endclass
myclass mc = new;
initial
repeat (10)
if(mc.randomize()==1)
$display("log1 = %0d log2=%0d log3=%0d
log4=%0d",mc.log1, mc.log2,
mc.log3, mc.log4);
endprogram
In this program block class myclass contains the following:
• Declarations for standard random variables, with the logic data
type and two bits, named log1, log2, and log3.
• A declaration for cyclic-random variable, with the logic data type
and two bits, named log4.
• Constraint c1 which says that the random values of log1 must be
greater than 0.
• Constraint c2 which says that the random values of log2 must be
less than 3.
The randomize() method is described in “Randomize Methods” on
page 24-100.
The $display system task displays the following:
log1 = 1 log2=1 log3=1 log4=2