User guide

24-69
SystemVerilog Testbench Constructs
Variable randc1 has two bits so its possible values range from 3 to
0. VCS derives a random order, or permutation, of all the possible
values, and assigns the values in the permutation in a sequence.
If VCS assigns a value of 3, it won’t assign 3 again until it first assigns
2, 1, and 0 (in no particular order), and after it assigns the permutation,
it derives the next permutation, beginning with any of the possible
values.
If this were a standard random variable, after VCS assigns the 3 value,
there is a 1/4 chance that VCS assigns the 3 again, but because it is
a random-cyclic variable, after VCS assigns the 3, there is no chance
that 3 will also be the next assigned value.
Random variables can only be declared in a class.
class Bus;
rand bit [15:0] addr;
rand bit [15:0] data;
.
.
.
endclass
Constraint Blocks
Constraints are specified in a constraint block. A constraint block can
be declared in the same class in which the random variables are
declared as well as in a class extended from the base class in which
the random variable is defined (see page 58 for definition of “base
class”) A constraint block begins with the keyword constraint.
program prog;