User guide

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SystemVerilog Testbench Constructs
Random Constraints
SystemVerilog has constructs for the random testing of a design and
a means of constraining the random testing to find hard to reach
corner cases.
Note:
To enable the new constraint features, use the -ntb_opts
new_constraints compile-time option.
Random Variables
You need variables to which VCS assigns random values. There are
two types of random variables and two different keywords to begin
their declarations:
rand
Specifies a standard random variable
randc
Specifies a random-cyclic variable.
The following is an example of a standard random variable
declaration:
rand bit [7:0] randbit1;
Variable randbit1 has eight bits so its possible values range from
0 to 255. The chances that VCS assigns any of these values is
precisely 1/256.
The following is an example of a random-cyclic variable declaration:
randc bit [1:0] randc1;