User guide

24-66
SystemVerilog Testbench Constructs
Class Packet Example
class Packet;
bit [3:0] command; //property declarations
bit [40:0] address;
bit [4:0] master_id;
integer time_requested;
integer time_issued;
integer status;
function new(); // initialization
command = 0;
address = 41’b0;
master_id = 5’bx;
endfunction
task clean(); //method declaration
command = 0;
address = 0;
master_id = 5’bx;
endtask
task issue_request(int delay); //method
// declaration send request to bus
endtask
function integer current_status(); //method
// declaration
current_status = status;
endfunction
endclass
Unpacked Structures in Classes
The following code examples shows an unpacked structure in a
class:
program test;