User guide

2-35
Modeling Your Design
Dealing With Unassigned Nets
Consider the following example:
module test(A);
input A;
wire A;
DUT DUT_1 (A);
// assign A = 1'bz;
initial
$lsi_dumpports(DUT_1,"dump.out");
endmodule
module DUT(A);
input A;
wire A;
child child_1(A);
endmodule
module child(A);
input A;
wire Z,A,B;
and (Z,A,B);
endmodule
In this case, the top level wire A is undriven at the top level. It is an
input which goes to an input in DUT_1, then to an input in CHILD_1
and finally to an input of an AND gate in CHILD_1. When
$lsi_dumpports evaluates the drivers on port A of test.DUT_1, it
finds no drivers on either side of port A of DUT_1, and therefore gives
a code of F, tristate (input and output unconnected).