User guide

24-59
SystemVerilog Testbench Constructs
class ClassA;
...
endclass
class Class_a extends ClassA;
...
endclass
class class_ab extends Class_a;
...
endclass
class Class_b extends ClassA;
...
endclass
Both Class_a and Class_b are extended from ClassA using the
extends keyword, making ClassA the base class for these two
subclasses. Class_ab extends from Class_a, making Class_a the
base class for the subclass, Class_ab. Both ClassA and Class_a are
super classes since they each have subclasses extended from them.