User guide

24-49

SystemVerilog Testbench Constructs

end

endprogram

The Output of this program is

Accessing enum label in constraint block through :: operator

e1 = S1

e1 = S2

e1 = S3

e1 = S1

Accessing enum label in function block through :: operator

e1 = S3

Class Extensions

Subclasses and Inheritance

SystemVerilog’s OOP implementation provides the capability of

inheriting all the properties and methods from a base class, and

extending its capabilities within a subclass. This concept is called

inheritance. Additional properties and methods can be added to this

new subclass.

For example, suppose we want to create a linked list for a class

“Packet.” One solution would be to extend Packet, creating a new

subclass that inherits the members of the parent class (see Class

Packet Example on page 66 for class “Packet” declaration).

class LinkedPacket extends Packet;

LinkedPacket next;

function LinkedPacket get_next();

get_next = next;

endfunction