User guide

24-40
SystemVerilog Testbench Constructs
Classes
The user-defined data type, class, is composed of data members of
valid SystemVerilog data types (known as properties) and tasks or
functions (known as methods) for manipulating the data members.
The properties and methods, taken together, define the contents and
capabilities of a class instance (also referred to as an object).
Use the class and endclass keywords to declare a class.
class B;
int q = 3;
function int send (int a);
send = a * 2;
endfunction
task show();
$display("q = %0d", q);
endtask
endclass
In the above example, the members of class “B” are the property, q,
and the methods send() and show().
Note:
- See “Class Packet Example” on page 24-66 for a more complex
example of a class declaration. The name of the class is
“Packet.”
- Unpacked unions inside classes are not yet supported. Packed
unions and packed and unpacked structures inside classes are
supported.
class myclass;
typedef struct packed{ int int1;