User guide

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SystemVerilog Testbench Constructs
assoc_array1[7]=3'b111;
foreach (assoc_array1[dim1])
$display("assoc_array1 [%1d]=%0d",
dim1,assoc_array1[dim1]);
end
endprogram
The $display system task displays the following:
assoc_array1 [0]=0
assoc_array1 [1]=1
assoc_array1 [7]=7
Array Aggregates (Reduction/Manipulation) Methods in
Constraints
SystemVerilog includes a set of array reduction methods which allow
declarations of complex constraints for arrays and queues in a
compact and flexible format.
The following is the syntax for these methods:
function array_or_expression_type method
(array_type iterator = item)
The array aggregate expression is a valid part of a constraint
expression and can be used any place that a variable can be used,
with the exception of solve-before constraints.