User guide

24-35
SystemVerilog Testbench Constructs
module test;
bit [11:10][9:8][7:0] bit_array1;
initial
begin
foreach (bit_array1[dim1,dim2])
bit_array1 [dim1][dim2]=dim1*dim2;
foreach (bit_array1[dim1, dim2])
$display("bit_array1[%1d][%1d]=%0d",
dim1,dim2,bit_array1[dim1][dim2]);
end
endmodule
The bit data type array named bit_array1 has three dimensions.
The first foreach loop iterates through the first two dimensions
11:10 and 9:8, to assign 8-bit values to these elements.
The second foreach loop displays the deposited values.
The $display system task displays the following:
bit_array1 [11][9]=99
bit_array1 [11][8]=88
bit_array1 [10][9]=90
bit_array1 [10][8]=80
The foreach loop also works with other types of arrays, such as this
example of a string array:
module test;
string words [2];
initial
begin
words [1] = "verification";
words [0] = "simulation";
foreach (words [j])
$display("string element number %1b",j,
"contains \"",words[j],"\"");
end