User guide

18-6
Translating VCD and VCD+
Options
Files
-h Translate hierarchy information only
-m Give translation metrics during the conversion
-s Allow sign extension for vectors. Reduces size of
<vcd.file>
+morevhdl Translate VHDL types that are not directly mappable to
verilog types. These VHDL types are in addition to the ones
that are directly mappable. See
VHDL Mapping.
+ignoredelta Leave delta cycle information out of the translation. This
improves efficiency when the VPD file contains delta cycle
information that you do not need in the VCD file.
+start+<value> Translate value changes starting after start time <value>.
+end+<value> Translate value changes ending before end time <value>.
vpd_file The VCD+ file that is to be converted VCD file.
vcd_file The VCD file generated from the VCD+ file.