User guide

1-6
VirSim Overview
Environment
OSF/Motif™ and
Windows NT™
You can run VirSim in either the OSF/Motif™ environment
or the Microsoft
Windows NT™ operating system. Most
screen examples in this manual show VirSim screens for
Windows NT. Where features and screen format differ
significantly, the manual also includes the OSF/Motif™
format. This manual assumes you have a working knowledge
of OSF/Motif or Windows NT.
Scope (Verilog) A scope is any instance of a module, task, function, or
named block in the Verilog Hardware Description Language
(HDL) source code. These structures are used to organize
and describe logical, structural, and functional groupings of
code. Modules can contain more modules, tasks, functions,
and named blocks. Tasks, functions, and named blocks can
only contain named blocks.
Scope (VHDL) In VHDL, a scope is any instance of an entity/architecture
component. (The entity/architecture component is
analogous to a module in the Verilog language.) Blocks,
Packages, Processes, Procedures, and Functions are also
considered scopes.
Variables and
Signals
(Verilog)
The term variables is used interchangeably with the term
signals. Variable was adapted from the standard VCD
technology and can refer to any of the following Verilog terms:
Net
Reg
Real Number
Integer
Named Event
Time Variable
Variables and
Signals
(VHDL)
The VHDL language distinguishes between signals and
variables. In general, VirSim uses the term signals to refer
to both signals and variables. There are some exceptions to
this rule, but these exceptions are either explicitly stated or
implied by the context of its usage. (For example, a dialog
that has both a selection for Signals and a selection for
Variables is obviously distinguishing between the two.) It is
also important to recognize that because most variables are
dynamic, simulators may not trace them and consequently
they will not show up in the hierarchy.
VCD+ VCD+ is a proprietary binary format for simulation history
data, which is generated by a PLI program linked to the
simulator. It is used for both Verilog and VHDL simulation