User’s Manual from Emerson Network Power ™ Embedded Computing PmT1 and PmE1: High Speed T1 and E1 Interface Module December 2007
The information in this manual has been checked and is believed to be accurate and reliable. HOWEVER, NO RESPONSIBILITY IS ASSUMED BY EMERSON NETWORK POWER, EMBEDDED COMPUTING FOR ITS USE OR FOR ANY INACCURACIES. Specifications are subject to change without notice. EMERSON DOES NOT ASSUME ANY LIABILITY ARISING OUT OF USE OR OTHER APPLICATION OF ANY PRODUCT, CIRCUIT, OR PROGRAM DESCRIBED HEREIN. This document does not convey any license under Emerson patents or the rights of others. Emerson.
Regulatory Agency Warnings & Notices The Emerson PmT1 and PmE1 meets the requirements set forth by the Federal Communications Commission (FCC) in Title 47 of the Code of Federal Regulations. The following information is provided as required by this agency. This device complies with part 15 of the FCC Rules.
Regulatory Agency Warnings & Notices (continued) This board is designed to be connected to the telephone network or premises wiring using a compatible modular jack which is Part 68 compliant. This board cannot be used on telephone company-provided coin service. Connection to Party Line Service is subject to state tariffs. If this board causes harm to the telephone network, the telephone company will notify you in advance that temporary discontinuance of service may be required.
Regulatory Agency Warnings & Notices (continued) Information shall be provided as to the power source requirements. See the PmT1 and PmE1 power requirements in the hardware manual. If the device is enclosed in an assembly, and not readily accessible, a label shall be placed on the exterior of the cabinet listing the registration number of each PmT1 and PmE1 contained therein. The final assembler shall provide, in the consumer instructions, all applicable Network Connection Information.
Regulatory Agency Warnings & Notices (continued) EC Declaration of Conformity According to EN 45014:1998 Manufacturer’s Name: Emerson Network Power Embedded Computing Manufacturer’s Address: 8310 Excelsior Drive Madison, Wisconsin 53717 Declares that the following product, in accordance with the requirements of 2004/108/EEC, EMC Directive and 1999/5/EC, RTTE Directive and their amending directives, Product: PMC Module Model Name/Number: PmT1 and PmE1/01439143-xx has been designed and manufactured
Contents 1 Overview 5 Serial I/O Components and Features . . . . . . . . . . . 1-1 Functional Overview . . . . . . . . . . . . . . . . 1-1 Physical Memory Map . . . . . . . . . . . . . . . 1-2 Additional Information . . . . . . . . . . . . . . 1-4 Product Certification . . . . . . . . . . . . . 1-4 RoHS Compliance. . . . . . . . . . . . . . . . 1-6 Terminology and Notation . . . . . . . . 1-6 Technical References. . . . . . . . . . . . . 1-6 2 Setup Electrostatic Discharge . . . . . . . . . . . . . .
Monitor Power-up/Reset Sequence . . . . . . . . . . . .8-1 Start-up Display . . . . . . . . . . . . . . . . . . . . .8-4 Command-line History . . . . . . . . . . . . . . .8-5 Command-line Editor . . . . . . . . . . . . . . . .8-5 Initializing Memory . . . . . . . . . . . . . . . . . .8-6 Command Syntax . . . . . . . . . . . . . . . . . . . .8-6 Initializing Memory . . . . . . . . . . . . . . . . . .8-7 Command Syntax . . . . . . . . . . . . . . . . . . . .8-7 Typographic Conventions . . . . . . . .
Contents (continued) TestSuite . . . . . . . . . . . . . . . . . . . . . .8-44 xprintf. . . . . . . . . . . . . . . . . . . . . . . . .
Contents viii (continued) PmT1 and PmE1 User’s Manual 10002367-02
Figures Figure 1-1: General System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Figure 1-2: Physical Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Figure 2-1: PmT1 and PmE1 Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Figure 2-2: Component Map, Top (rev. 33) . . . . . . . . . . . . . . . . . . .
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Tables Table 1-1: Address Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Table 1-2: MTBF Hours . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Table 1-3: Regulatory Agency Compliance — T1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Table 1-4: Regulatory Agency Compliance — E1 . . . . . . . . . . . . . .
xii Table 7-9: Connector P11 and P12 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 Table 8-1: NVRAM Configuration Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 Table 8-2: Device Download Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 Table 8-3: NVRAM Power-up Diagnostic PASS/FAIL Flags . . . . . . . . . . . . . . . . . . . . . . . .
Registers Register 4-1: Board Configuration 0 (BCR), 0x010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Section 1 Overview The PmT1 and PmE1 is a single width PMC module designed to provide high-speed T1 and E1 interfaces for PMC-compatible baseboards. The design is based on the Freescale™ MPC860P PowerQUICC™ microprocessor and the PLX Technology PCI9060ES bus interface controller. The PmT1 has two standard landed T1 channels, and the PmE1 has two standard landed E1 channels. An optional EIA-422 port is available.
Overview: Physical Memory Map Figure 1-1: General System Block Diagram PmT1 or PmE1 Channel 1 CPU MPC860P System Interface Unit (SIU) PmT1 or PmE1 Channel 2 or EIA422 Port 32-Bit Bus Power PC Processor Core PMC Connectors P14 Memory Controller Internal External Bus Interface Bus Interface Unit Unit System Functions Real-Time Clock PCMCIA-ATA Interface Communcations Processor Module (CPM) EIA232 Console and Download Serial Ports I2C A32/D32 DRAM 16 megabytes Flash/ROM Socket 512 kilobytes PCI Con
Overview: Physical Memory Map Figure 1-2: Physical Memory Map Hex Address FFFF,FFFF FFF0,0000 Flash/ROM Socket CPU Registers FF00,0000 Reserved C101,0000 C100,0000 C000,0200 C000,0180 C000,0080 C000,0000 PMC/PCI Interface Registers Reserved Board Configuration Register Reserved IDs / Interrupts Reserved 8000,0000 PCI I/O Space 6000,0000 PCI Memory Space 4000,0000 Reserved 0100,0000 DRAM 0000,0000 10002367-02 PmT1 and PmE1 User’s Manual 1-3
Overview: Additional Information Table 1-1: Address Summary Physical Address (hex): Access Mode: Description: See Page: FFF0,0000 R Flash/ROM Socket 4-1 FF00,0000 R/W CPU registers 3-2 C101,0000 — reserved — C100,0000 R/W PMC/PCI Interface registers 7-2 C000,0200 — reserved — C000,0180 R Board Configuration register 4-3 C000,0080 — reserved — C000,000C R Conventional Interrupt register 3-4 C000,0000 R Interrupt Vector register 3-4 8000,0000 — reserved — 6000,00
Overview: Additional Information Table 1-3: Regulatory Agency Compliance — T1 Type: Specification: Safety UL60950-1, CSA C22.2 No.
Overview: Additional Information RoHS Compliance The PmT1 and PmE1 are compliant with the European Union’s RoHS (Restriction of Use of Hazardous Substances) directive created to limit harm to the environment and human health by restricting the use of harmful substances in electrical and electronic equipment.
Overview: Additional Information Device / Interface: Document: 1 EEPROM CAT93C86 (Die Rev. C) 16-Bit Microwire Serial EEPROM (Catalyst l Semiconductor, Inc.., Doc. No. 1091, Rev. O, 10/13/06) http://www.catsemi.com/ PCI PCI Local Bus Specification (PCI Special Interest Group, Revision 2.1 1995) http://www.pcisig.com/ (continued) PCI9060ES PCI Bus Master Interface Chip for Adapters and Embedded Systems–data sheet (Mountain View, CA: PLX Technology, Inc., December1995 VERSION 1.2) http://www.plxtech.
Overview: 1-8 Additional Information PmT1 and PmE1 User’s Manual 10002367-02
Section 2 Setup This chapter describes the physical layout of the boards, the setup process, and how to check for proper operation once the boards have been installed. This chapter also includes troubleshooting, service, and warranty information. ELECTROSTATIC DISCHARGE Before you begin the setup process, please remember that electrostatic discharge (ESD) can easily damage the components on the PmT1 and PmE1 hardware.
Setup: PmT1 and PmE1 Circuit Board Figure 2-2: Component Map, Top (rev.
Setup: PmT1 and PmE1 Circuit Board Figure 2-3: Component Map, Bottom (rev.
Setup: Installation Connectors The PmT1 and PmE1 circuit board has various connectors (see the figures beginning on page 2-2), summarized as follows: P1/P2: These connectors are installed for the PmT1 front panel I/O configurations. See Chapter 6 for pin assignments. P3: This is the optional 10-pin BDM JTAG header for viewing processor functions. See Table 3-7 for pin assignments. P11/P12: These provide a 32-bit PCI interface between the module and the PMC baseboard.
Setup: PmT1 and PmE1 Setup Figure 2-4: PmT1 and PmE1 Installation Voltage key Tighten these two screws first. 4 Insert and tighten the two remaining screws.
Setup: Reset Methods Table 2-2: Power Requirements Volts: Range (volts): Maximum Current: +5 +/- 5% 1.16 A, typical1 1. Running on-card memory test. The exact power requirements for the PmT1 and PmE1 circuit board depend upon the specific configuration of the board, including the CPU frequency and amount of memory installed on the board. Please contact Emerson Technical Support at 1-800-327-1251 if you have specific questions regarding the board’s power requirements.
Setup: Troubleshooting ❐ Be sure the PmT1 and PmE1 circuit board is seated firmly in the baseboard and that the baseboard is fully plugged in the chassis. ❐ Be sure the system is not overheating. ❐ Check the cables and connectors to be certain they are secure. ❐ If you are using the PmT1 and PmE1 monitor, run the power-up diagnostics and check the results. “Power-up Diagnostic/Test Commands”, Section describes the power-up diagnostics. ❐ Check your power supply for proper DC voltages.
Setup: Troubleshooting • license agreements (if applicable) Serial number 10001234-AA YYYYY 590- YYYYY Product ID 10001234-AA D D Figure 2-5: Serial Number and Product ID on Bottom Side 590- Product Repair If you plan to return the board to Emerson Network Power for service, visit http://www.emersonembeddedcomputing.com/contact/productrepair.html on the internet or send e-mail to serviceinfo@artesyncp.com to obtain a Return Merchandise Authorization (RMA) number.
Section 3 Central Processing Unit The PmT1 and PmE1 module uses the Freescale MPC860P PowerQUICC™ microprocessor installed as its CPU. The MPC860P combines an embedded PowerPC™ core with features of the QUICC MC68360 communications processor module (CPM). This chapter is an overview of the processor logic on the PmT1 and PmE1. It includes information on the CPU, exception handling, and processor reset.
Central Processing Unit: MPC860P Initialization Table 3-2: MPC860P Special Purpose Register Initialization Decimal Address: Register: Required Hex Format: Notes: 148 ICR 0000,0000 Interrupt cause 149 DER 0000,0000 Debug enable 158 ICTRL 0000,0000 Instruction support control 638 IMMR FF00,0000 Internal memory map sets up the base address of the MPC860P internal register block — MSR 1002 Machine State register (control) The internal registers of the MPC860P are mapped to a contiguou
Central Processing Unit: MPC860P Exception Handling Physical Address (hex): Register: Required Hex Format: Description: FF00,0950 PADIR 000A Port A data direction register (continued) FF00,0952 PAPAR 0000 Port A pin assignment register FF00,0954 PADDR 0000 Port A open drain register FF00,09F0 BRGC1 10144 BRG1 configuration register FF00,09F4 BRGC2 10144 BRG2 configuration register FF00,0A82 SMCMR1 4823 SMC1 mode register FF00,0A92 SMCMR2 4823 SMC2 mode register FF00,0AB8
Central Processing Unit: System Interface Unit (SIU) Exception: Vector Address Hex Offset: Data TLB error 01400 Data breakpoint 01C00 Peripheral breakpoint 01E00 External interrupt 00500 Decrementer Decrementer Notes: (continued) Lowest priority CPU Interrupts The logic on the PmT1 and PmE1 module receive external interrupts LSERR* and LINTo* from the PCI9060ES chip. These interrupts are combined on IRQ7*, which is the only external interrupt input used on the MPC860P.
Central Processing Unit: Software Reset Physical Hex Address: Acronym: Register Block Name: FF00,0200 — System integration timers FF00,0280 — Clocks and reset FF00,0300 — System integration timers keys FF00,0380 — Clocks and reset keys (continued) Timebase Counter This 64-bit counter provides a timebase reference for software. The counter generates a maskable interrupt when it reaches the value programmed into one of four reference registers.
Central Processing Unit: Optional BDM Header Table 3-6 lists the implementation of the MPC860 Port A and C signals used on the PmT1 and PmE1 module.
Central Processing Unit: Optional BDM Header Figure 3-1: Processor BDM Header 10 2 9 1 Table 3-7: Processor BDM Pin Assignments Pin Number: Signal Name: 1 VFLSO Visible History Buffer Flushes Status 0 output line reports how many instructions were flushed from the history buffer in the MPC860P internal core. 2 SRESET* Software Reset input signal may initiate a warm reset.
Central Processing Unit: 3-8 PmT1 and PmE1 User’s Manual Optional BDM Header 10002367-02
Section 4 On-Card Memory Configuration The PmT1 and PmE1 module provides one 32-pin flash socket, an EEPROM, and one RAM configuration. Off-card memory may be accessed via the PMC/PCI interface. SOCKETED FLASH The PmT1 and PmE1 modules have a 32-pin PLCC socket for a byte-wide read-only flash. Up to 512-kilobytes of flash may be installed. The socketed flash occupies physical address space FFF0,0000-FFFF,FFFF16. Note: To avoid damage, please use the proper tool to remove the PLCC device.
On-Card Memory Configuration: On-card DRAM I2C EEPROM Operation The I2C EEPROM supports a bidirectional bus-oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is the CPU, and the I2C EEPROM being controlled is the slave. The CPU always initiates data transfers and provides the clock for both transmit and receive operations.
On-Card Memory Configuration: On-card DRAM On-card Memory Sizing and Type The Board Configuration register (C000,018016) is a byte-wide, read-only register that contains configuration information about the MPC860P and DRAM. Bit (5) is no parity. The configuration registry values are factory set. Register 4-1: Board Configuration 0 (BCR), 0x010 7 6 LBS 5 4 3 2 1 0 1 0 MEMS NOB MEMS NOB LBS: Local Bus Speed 00 Reserved 01 33.33 MHz with 66.66 MHz processor 10 40.00 MHz with 40.
On-Card Memory Configuration: Cycle: Total Clocks: Burst Write (4 accesses) 7 1 5 2 On-card DRAM Wait States: (continued) 1 2-1-1-1 2 2-1-1-1 1. At 40 MHz local bus speed. 2. At 33 MHz local bus speed. For non-burst cycles, the number in the “Total Clocks” column of Table 4-3 is the total number of CPU clock cycles required to complete the transfer, and the number in the “Wait States” column is the number of wait states per cycle.
Section 5 Serial I/O The PmT1 and PmE1 module has six TTL serial ports that are supplied by the MPC860P PowerQUICC™.
Serial I/O: The Communications Processor Module CPM Register Initialization Format Some of the CPM registers must be initialized as described in Table 5-2.
Serial I/O: The Communications Processor Module Priority: Lowest Function: Description: 4 SCC1 Reception 5 SCC1 Transmission 6 SCC2 Reception 7 SCC2 Transmission 8 SCC3 Reception 9 SCC3 Transmission 10 SCC4 Reception 11 SCC4 Transmission 12 SMC1 Reception 13 SMC1 Transmission 14 SMC2 Reception 15 SMC2 Transmission 16 reserved 17 reserved 18 reserved 19 RISC Timers CPM Interrupt Handling The CPM RISC controller generates interrupts through the interrupt controller to the
Serial I/O: MPC860P Serial Interface General Purpose Timers The general purpose timers can be configured as four 16-bit or two 32-bit identical timers. The best resolution of the time is one clock cycle, which translates to 25 nanoseconds at 40 MHz. The maximum period is 268,435,456 cycles, translating to 6.7 seconds at 40 MHz. Independent DMA (IDMA) Channels The MPC860P has two IDMA channels which may be programmed by the user to transfer data between any combination of memory and I/O.
Serial I/O: MPC860P Serial Interface Serial Communication Controllers (SCC) The MPC860P has four SCCs which may be configured independently to implement different protocols. Protocols such as UART, HDLC, and SS7 are supported to varying degrees in the MPC860P. The choice of protocol is independent of the choice of physical interface. The SCCs do not implement the physical interface. They are connected to the outside world via the serial interface (SI).
Serial I/O: UART Baud Rate Selection • frames up to 8-kilobits long UART BAUD RATE SELECTION The clock sources for each SCC are defined in the SICR register (FF00,0AEC16) and for each SMC are defined in the SIMODE register (FF00,0AE016). Any one of four internal baud rate generators or an external clock may be used. The internal baud rate generators are contained in the CPM. They can deliver a maximum baud rate at one half of the system clock rate and may be changed on-the-fly.
Serial I/O: Serial Connector Pin Assignments System Frequency=40 MHz (continued) Baud Rate: Div16 Value: Clock Divider + 1: Actual Frequency: Frequency Error (%): 76800 1 33 75757.6 1.4 Note: The EIA-232C specification defines a maximum rate of 20,000 bits per second over a typical 50-foot cable (2,500 picofarads maximum load capacitance). Higher baud rates are possible, but successful operation depends specifically upon the application, cable length, and overall signal quality.
Serial I/O: Serial Connector Pin Assignments P14 Pin: P0 Pin: P2 Pin: Signal: P14 Pin: P0 Pin: P2 Pin: Signal: 13 — — — 14 B6 A7 GND 15 A6 C8 TDM#2 TxTip1 16 E7 A8 17 — — — 18 C7 A9 19 B7 C10 20 A7 A10 TDM#2 TxRing 1 TDM#2 RxTip 1 TDM#1 TxTip 22 — — — 24 B8 A12 TDM#1 RxRing RS422 TXD+ 1 21 E6 C11 23 C8 C12 1 TDM#2 RxRing 1 TDM#1 TxRing 1 TDM#1 RxTip 25 A8 C13 RS422 TXD-* 26 E12 A13 27 — — — 28 C12 A14 RS422 RXD+ 29 B12 C15 RS422 RXD-*
Section 6 TDM Interface The Time Division Multiplexor (TDM) processes channelized serial data such as T1 and E1. The data channels can be routed internally to the QUICC to any of the SCC or SMC controllers. Each port can be configured to be either T1 or E1 at manufacturing.
TDM Interface: Table 6-2: T1E1 Signals from Transceiver, P1 P1 Pin: Signal Name: P1 Pin: 1 RRING 2 Signal Name: RTIP 3 no connect 4 TRING 5 TTIP 6 no connect 7 no connect 8 no connect Table 6-3: TDM to T1E1 Port Connections for TDMA (P2) QUICC Pins to Transceiver: Direction: DS215xQ Function: PA(9) L1TXDA TSER PA(5) L1TCLKA TCLK PC(5) L1TSYNCA TSYNC PA(8) L1RXDA RSER PA(7) L1RCLKA RCLK PC(4) L1RSYNCA RSYNC Table 6-4: T1E1 Signals from Transceiver, P2 P2 Pin: Sign
TDM Interface: Figure 6-1: TDM and FDL Connectivity Diagram TDMA QUICC BRG02 FDLA L1TSYNCA (PC5) TSYNC L1RSYNCA (PC4) RSYNC L1TXDA (PA9) TSER L1RXDA (PA8) RSER DS2151Q L1RCLKA (PA7) CLK1 CLK2 (PA6) RCLK PmT1 L1TCLKA (PA5) BRG02/CLK3 TCLK or DS2153Q TXD1 (PA14) TLINK RXD1 (PA15) RLINK TLCLK RLCLK TDMB BRG04 L1TSYNCB (PC7) TSYNC L1RSYNCB (PC6) RSYNC PmE1 Channel 0 L1TXDB (PA11) TSER L1RXDB (PA10) RSER DS2151Q L1RCLKB (PA2) CLK6 RCLK PmT1 L1TCLKB (PA0) CLK8 TCLK or P1
TDM Interface: The T1 or E1 Line Interface TCLK: The transmit clock must be driven to the T1 or E1 controller. The clock will be driven by a baud rate generator. In this case, the baud rate generator is driven by the RCLK input or system clock. The TCLK line for TDM channel 'B' is routed to BRG04 to support this option. TSYNC RSYNC: The data signals must always be driven by the T1 or E1 controller.
TDM Interface: Configuring the T1 or E1 Interface CONFIGURING THE T1 OR E1 INTERFACE The PmT1 and PmE1 framers have typical configuration settings for operation.
TDM Interface: The T1 FDL Interface Depending on the configuration of the board, the FDL receiver can be connected to an SCC allowing the application to push the overhead of receive data on the QUICC chip. However, the transmitter can only be accessed via the FDL transmit register. The only exception is when the transmitter and receiver can be made multi-frame synchronized.
TDM Interface: The Management Data Interface (MDI) THE MANAGEMENT DATA INTERFACE (MDI) The MDI or Management Data Interface is a 3-wire protocol which allows access to the module resources, registers and interrupts using the minimum resources necessary. This interface consists of Data (MDIO), Clock (MDCLK) and Interrupt (MDINT) lines. The MDI uses control pins PC0-PC2, which are not likely to conflict with any MPC860P dedicated functions.
TDM Interface: Front Panel I/O Table 6-7: MDI Bit Field Format Field: Width: Function 1: Start 2 The “01” transition frames the beginning of an MDI cycle. The MDI Interface is reset when the MDIO line (which is pulled up) is high for greater than 40 clocks.
TDM Interface: Front Panel I/O The recommended cable assembly (Emerson part number C308A009-05) for P1 and P2 is shown in Fig. 6-4. The manufacturer part numbers for these connectors are Stewart Connector Systems SS-310808-5 and SS-800810-040-250. See Table 6-8 for the Compu-Shield and RJ-45 jack pin assignments.
TDM Interface: 6-10 PmT1 and PmE1 User’s Manual Front Panel I/O 10002367-02
Section 7 PMC/PCI Interface The PmT1 and PmE1 module design complies with the Peripheral Component Interconnect (PCI) bus interface standard and with the associated PCI Mezzanine Card (PMC) mechanical interface standard. The PmT1 and PmE1 modules must be attached to and controlled by a PMC/PCI-compliant baseboard. The PmT1 and PmE1 use the PLX Technology PCI9060ES interface controller to implement the +5V PMC/PCI interface.
PMC/PCI Interface: PCI9060ES Register Map Local Bus Address (hex): PCI Offset Address (hex): Size: Register Name: (continued) C100,000C 0C Byte PCI Cache Line Size register C100,000D 0D Byte PCI Latency Timer register C100,000E 0E Byte PCI Header Type register C100,000F 0F Byte PCI Built-in Self Test (BIST) register C100,0010 10 Long PCI Base Address register (for memory access to Local Configuration and Shared Runtime registers) C100,0014 14 Long PCI Base Address register (for
PMC/PCI Interface: PCI9060ES Initialization Local Bus Address (hex): PCI Offset Address (hex): Size: Register Name: (continued) C100,00A0 20 Long Local Bus Base Address register (Direct Master to PCI memory) C100,00A4 24 Long Local Base Address For Direct Master to PCI I/O/CFG register C100,00A8 28 Long PCI Base Address register (Direct Master to PCI) C100,00AC 2C Long PCI Configuration Address register (Direct Master to PCI IO/CFG) Shared Runtime Registers The Shared Runtime registers
PMC/PCI Interface: PCI9060ES Initialization The serial EEPROM may be reprogrammed to configure the PCI bridge in other ways. Bits (27:24) of the PCI9060ES EEPROM control register (C100,00EC16) are used for reading and writing the EEPROM. Refer to the NS93CS46 data sheet listed in Table 1-5 for a description of the EEPROM’s programming instructions, and the PCI9060ES data sheet for the sequence in which the data is stored.
PMC/PCI Interface: PCI9060ES Initialization Table 7-5: PCI9060ES Local Configuration Register Initialization 1 Local Bus Address (hex): Register: Hex Value at the byte-swapped PCI9060ES: at the CPU: Notes: C100,0080 Local Address Space 0 Range FF800008 080080FF Memory space reads are prefetchable. The PCI-to-local range is set to 2MB of on-card DRAM. C100,0084 Local Space 0 Local Base Address 00000001 01000000 PCI-to-local remap address is 0000,000016. Enable PCI-to-local accesses.
PMC/PCI Interface: PCI9060ES Initialization Table 7-6: PCI9060ES Shared Runtime Register Initialization Local Bus Address (hex): Register: Hex Value at the byte-swapped PCI9060ES: at the CPU: C100,00C0 Mailbox 0 00000000 00000000 These registers are initialized by the serial EEPROM. C10000C0 will be a5000000 upon successful completion of the Monitor power up diagnostics. C100,00C4 Mailbox 1 00000000 00000000 These registers are initialized by the serial EEPROM.
PMC/PCI Interface: PCI9060ES Initialization Table 7-7: PCI9060ES Bus Priority Control Hex Address: Bits: Register Field: Factory Default Value (hex): C100,0094 3:0 Direct Slave BREQo Delay Clocks 1 (8 clocks) C100,0094 4 Local Bus BREQo Enable 1 (BREQo enabled) C100,0098 31:28 PCI Target Retry Delay Clocks F (120 clocks) As an example, a user could give priority to the Direct Slave device (PCI bus) by enabling the BREQo timer and setting Direct Slave BREQo Delay Clocks to a value less tha
PMC/PCI Interface: PCI Interrupts Managing Bandwidth It is possible to inadvertently set the PCI9060ES to give a disproportionate bandwidth on either side of the bridge. For instance, one side may retry frequently because the timer value is slightly less than the time required to gain access to the other side. As a result, the retries needlessly consume a large percentage of the attempted cycles. To avoid this situation, tune the timer values appropriately for the system devices.
PMC/PCI Interface: PMC Connector Pin Assignments Amp 120534-1, Molex 53483-0649 or Molex 53508-0648. The recommended mating connectors include Amp 120521-1, Amp 120528-1, and Molex 52763-0649. Refer to Fig. 2-1 for the placement of these connectors on the PmT1 and PmE1 module. Figure 7-1: PMC Interface Connectors (P11, P12, P14) 1 63 64 2 The PCI interface signals are routed out P11 and P12. Pin assignments for this interface are listed in Table 7-9. The serial I/O interface is routed out P14.
PMC/PCI Interface: PMC Connector Pin Assignments Pin: P11 Signal: P12 Signal: Pin: P11 Signal: P12 Signal: 51 GND AD07 52 C/BE0* no connect 53 AD06 no connect 54 AD05 no connect 55 AD04 no connect 56 GND GND 57 +5V no connect 58 AD03 no connect 59 AD02 GND 60 AD01 no connect 61 AD00 no connect 62 +5V no connect 63 GND GND 64 no connect no connect PCI Bus Control Signals The following signals for the PCI interface are available on connectors P11 and P12.
PMC/PCI Interface: PMC Connector Pin Assignments LOCK*: LOCK sustained tri-state signal indicates that an atomic operation may require multiple transactions to complete. PAR: PARITY is even parity across AD00-AD31 and C/BE0-C/BE3*. Parity generation is required by all PCI agents. This tri-state signal is stable and valid one clock after the address phase, and one clock after the bus master indicates that it is ready to complete the data phase (either IRDY* or TRDY* is asserted).
PMC/PCI Interface: 7-12 PmT1 and PmE1 User’s Manual PMC Connector Pin Assignments 10002367-02
Section 8 Monitor The PmT1 and PmE1 monitor consists of a set of about 150 C language functions. The monitor commands constitute a subset of these functions and are designed to provide easy-touse tools for PmT1 and PmE1 configurations at power-up or reset and communications, downloads, and other common uses. This chapter includes an introduction to monitor operation, instructions for command sequences that configure the PmT1 and PmE1 modules, a command reference, and a function reference.
Monitor: Power-up/Reset Sequence 6 The countdown to autoboot begins if a boot device (BootDev) is specified. If you allow the countdown finish, the selected device is booted. Reference page 8-7 for booting from specific devices using the boot commands. If you cancel configuration before the autoboot begins, the board is configured with the default nonvolatile configuration, which is summarized in Table 8-1. The configuration groups may be accessed with the NVRAM commands described on page 8-13.
Monitor: Power-up/Reset Sequence Fields: Purpose: Factory Default: RomBase Define ROM base. 0xfff30000 This field is used only when BootDev is defined as ROM. RomSize Define ROM size. 0x40000 This field is used only when BootDev is defined as ROM. DevType Define device type. 0 Whether you use this field depends on the application. When BootDev is defined as Bus or ROM, DevType refers to a device type.
Monitor: Start-up Display START-UP DISPLAY At power-up or after a reset, the monitor runs diagnostics and reports the results in the start-up display. The PmT1 and PmE1 displays have identical diagnostic reports.
Monitor: Command-line History You can cancel both the nonvolatile configuration sequence and the autoboot sequence by pressing the H key on the console keyboard before the boot ends. The monitor is then in a “manual” mode from which you can execute commands and call functions. The monitor also enters manual mode if the autoboot fails. Instructions for downloading and executing remote programs are given in the command reference and function reference.
Monitor: Initializing Memory ce or cE: Change text to the end of a word (capital E ignores punctuation). cb or cB: Change the word before the cursor (capital B ignores punctuation). c$: Change text from the cursor to the end of the line. d: Delete. Use additional commands with d to delete words or groups of words, as shown below. dw or dW: Delete a word after the cursor (capital W ignores punctuation). de or dE: Delete to the end of a word (capital E ignores punctuation).
Monitor: Initializing Memory INITIALIZING MEMORY The monitor uses the area between 0000,000016 and 0001,000016 for interrupt vector, stack, data, and bss space. Any writes to that area can cause unpredictable operation of the monitor. The monitor initializes all local memory on power-up and/or on reset, depending on the configuration of nonvolatile memory. The monitor initializes (i.e.
Monitor: Boot Commands unsigned long CallAddress; }; The structure consists of two unsigned long locations. The first is used for synchronization, and the second is the entry address of the application. The sequence of events used for loading an application is described below: 1 The host board waits for the target (this board) to write the value 0x496d4f6b (character string “ImOk”) to “MagicLoc” to show that the target is initialized and waiting for a download.
Monitor: Boot Commands bootrom is an autoboot device that allows you to boot an application program from ROM. It copies code from ROM into RAM and then jumps to the RAM address. The ROM source address RomBase, the RAM destination address LoadAddress, and the number of bytes to copy RomSize are read from the nonvolatile memory group BootParams. Description: bootrom When the application is called, two parameters are passed to the application from the nonvolatile memory group BootParams.
Monitor: Help Commands Also refer to the function BootUp on page 8-37. HELP COMMANDS help Use the help command to view the description of the monitor command specified by name. The full name of the command must be given. Description: help name For instructions on editing command lines, type help For a list of command-line functions, type help editor. functions. For a detailed memory map, type help memmap.
Monitor: Memory/Register Commands Description: copymem source destination bytecount displaymem displays memory in 16-byte lines starting at address startaddr. The number of lines displayed is determined by lines. If the lines argument is not specified, sixteen lines of memory are shown. The data is displayed as hex character values on the left and printable ASCII equivalents on the right. Nonprintable ASCII characters are printed as a dot.
Monitor: Memory/Register Commands setmem allows memory locations to be modified starting at address. setmem first displays the value that was read. Then you can type new data for the value or leave the data unchanged by entering an empty line. If you press after the data, the address counts up. If you press after the data, the address counts down. To quit this command type any illegal hex character (for example, “.”[period]).
Monitor: NVRAM Commands writestr writes the ASCII string specified by string to a memory location specified by address. The string must be enclosed in double quotes (“ “). Description: writestr “string” address NVRAM COMMANDS The monitor uses the I2C EEPROM for nonvolatile memory. A memory map of the I2C EEPROM is given in Table 4-2 earlier in this manual. Portions of this nonvolatile memory are reserved for factory configuration and identification information and the monitor.
Monitor: NVRAM Commands Group ‘Console’ PortA(A, B) Baud9600 ParityNone(Even, Odd, None, Force) Data8-bits(5-Bits, 6-Bits, 7-Bits, 8-Bits) StopBits2-bits(1-Bit, 2-Bits) ChBaudOnBreakFalse(False, True) RstOnBreakFalse(False, True) [SP, CR to continue] or [E, e to Edit] 3 Press E to edit the group. 4 Press until the field you want to change is displayed. 5 Type a new value. For most fields, legal options are displayed in parentheses. 6 Press or Q to quit the display.
Monitor: NVRAM Commands Description: nvset group field value To modify the list with the nvset command, you must specify the group and field to be modified and the new value. The group, field, and value can be abbreviated, as in the examples below: Example: =>nvset console port A =>nvset con dat 6 nvupdate attempts to write the Emerson- and monitor-defined nonvolatile sections back to the EEPROM. First the data is verified, and then it is written to the device.
Monitor: NVRAM Commands DevNumber0 ClrMemOnBootFalse(False, True) [SP, CR to continue] or [E, e to Edit] 3 Press E to edit the group. 4 Press until the BootDev field is displayed. 5 Type the new value ROM. 6 Press to display the LoadAddress field. 7 Type the address where execution begins. 8 Press to display the ROMBase field. 9 Type the ROM base address. 10 Press to display the ROMSize field. 11 Type the ROM size. 12 Press or Q to quit the display.
Monitor: Power-up Diagnostic/Test Commands POWER-UP DIAGNOSTIC/TEST COMMANDS The following on-card functional tests are available to be run at any time, including powerup and reset. The nonvolatile configuration memory can be used to enable or disable the execution of these tests on power-up and reset (see the nvdisplay command’s Misc group in Table 8-1). The results of the tests are stored at an offset of 0x60 in the I2C EEPROM.
Monitor: Remote Host Commands cachetest tests the operation of the data cache. The test writes a word to every cache line and verifies that the data was written into the data cache and not into DRAM. Description: cachetest eepromtest checks the interface to the I2C EEPROM by writing a byte to the device, and then reading it back and verifying the data. Description: eepromtest memtest performs an address boundary test throughout all of DRAM. The test first clears all of memory by writing zeros.
Monitor: Remote Host Commands pile, initiate and complete the download, and return to the monitor, all from one terminal. This is convenient for downloading, because a single control sequence issues a carriage return to the host and issues a download command to the PmT1 and PmE1. call allows execution of a program after a download from one of the board’s interfaces. This command allows up to eight arguments to be passed to the called address from the command line.
Monitor: Remote Host Commands Note: If you download from a UNIX host in binary format, be sure to disable the host from mapping to . The download port is specified in the nonvolatile memory configuration. transmode provides an interface to UNIX® through the board by connecting the console to a download port. A null modem cable might be necessary for the connection.
Monitor: Remote Host Commands 3 Press E to edit the group. 4 Press until the Baud field is displayed. 5 Type a new value. 6 Change other fields in the same way. 7 over all fields whether you edit them or not, until the monitor prompt reappears. 8 Type nvupdate to save the new value. Hex-Intel Format Hex-Intel format supports addresses up to 20 bits (one megabyte). This format sends a 20bit absolute address as two (possibly overlapping) 16-bit values.
Monitor: Remote Host Commands Here, the first 02 is the byte count (only the data in the ssss field is 3counted). 0000 is the address field; in this record the address field is meaningless, so it is always 0000. The second 02 is the record type; in this case, an extended address record. cs is the checksum of all the fields except the initial colon. Example: =>:020000020020DC In this example, the segment address is 002016.
Monitor: Remote Host Commands 01is the record type. FFis the checksum. This is the end-of-file record, which must be the last record in the file. It is the same for all output files.
Monitor: Remote Host Commands indicates that the start address segment value is one, and the start address offset value is 2, so the absolute start address is 1216. =>:04003000902BB4FD60 loads byte 9016 to address 4016 loads byte 2B16 to address 4116 loads byte B416 to address 4216 loads byte FD16 to address 4316 =>:00000001FF terminates the file. Motorola S-record Format S-records are named for the ASCII character “S,” which is used for the first character in each record.
Monitor: Remote Host Commands S1-S2-and S3-records (Data Records) S1nnaaaad1d2d3...dncs S2nnaaaaaad1d2d3...dncs S3nnaaaaaaaad1d2d3...dncs Where: S1 indicates the record type nn is the count of data and checksum bytes a...a are the data bytes cs is the checksum These are data records. They differ only in that S1-records have 16-bit addresses, S2records have 24-bit addresses, and S3-records have 32-bit addresses.
Monitor: Remote Host Commands S7-S8-and S9-records (Termination and Start Address Records) S705aaaaaaaacs S804aaaaaacs S903aaaacs Where: S7, S8, or S9 indicates the record type 05, 04, 03 count of address digits and the cs field a...a is a 4-, 6-, or 8-digit address field cs is the checksum These are trailing records. There can be only one trailing record per file, and it must be the last record in the output file.
Monitor: Utilities byte FA 16 to address 0916 byte FF16 to address 0A16 byte FE16 to address 0B16 S5030001FB indicates that only one S1-record, S2-record, or S3-record was sent. S9030008F4 indicates that the start address is 0000000816. UTILITIES configboard configures the board to the state specified by the nonvolatile memory configuration. This includes the serial ports, and processor caches, if necessary.
Monitor: Errors and Screen Messages mul multiplies two integers in decimal (the default), binary, octal, or hexadecimal from the monitor. The default numeric base is decimal. Specify hex by typing “:16” at the end of the value, octal by typing “:8” or binary by typing “:2.” The result of the operation is displayed in hex, decimal, octal, and binary. Definition: mul number1 number2 rand is a linear congruent random number generator that uses a function Seed and a variable Value.
Monitor: Monitor Function Reference Message: Source and Suggested Solution: No help for ___ The topic for help was misspelled or is not available. Check the spelling. If the topic was a command name, use the help command to check the spelling of the command. You must use the full command name, not an abbreviation. Power-up Memory Test FAILED A failed memory test could mean a hardware 1 malfunction. Unknown boot device The boot device is invalid.
Monitor: PmT1 and PmE1-Specific Functions Unlike the monitor commands, no argument checking takes place for functions that are called directly from the command line. PMT1 AND PME1-SPECIFIC FUNCTIONS ChangeBaud ChangeBaud(Baud, Port) struct SCCPort *Port; int Baud; ConfigSerDevs() Description: The function ChangeBaud allows the baud rate for the port defined by Port to be modified to the value defined by Baud.
Monitor: PmT1 and PmE1-Specific Functions KBHit(void) RKBHit() TxMT() RTxMT() Description: These functions provide the low-level I/O necessary to read, write, and configure the MPC860P. These functions are used to interface to both the console and modem device specified by the argument Port. The getchar function reads a character from specified device Port. This function is also set up to check for a break and allows the monitor to perform functions like reset or baud changes when a break is detected.
Monitor: PmT1 and PmE1-Specific Functions Description: This is a collection of miscellaneous board support functions. The functions MemTop and MemBase are used to determine the addresses of the last and first long words in free memory. The size of DRAM is determined by the configuration register. The base of free memory is determined by the compiler-created variable End, which indicates the end of the monitor’s bss section. The time_delay function provides a fixed delay for timing.
Monitor: MPC860P-Specific Functions The Cnt indicates the byte location to be modified and assumes the nonvolatile memory is a linear array of memory locations. If there are gaps between bytes on the physical device, they are dealt with here. The last parameter Val is a pointer to the character location to be written. This function returns the number of bytes written to the device or the value read from the device, depending on Mode. Only bytes that differ are written.
Monitor: MPC860P-Specific Functions typedef struct { HANDLER handler; HANDLERPARM parameter; }HANDLERSTRUCT; HANDLERSTRUCT ConnectHandler(unsigned long Vector, HANDLER Handler) ConnectHandler(Vector, Handler) unsigned long Vector; int (*Handler)(); DisConnectHandler(Vector) unsigned long Vector; probe(DirFlag, SizeFlag, Address, Data) char DirFlag, SizeFlag; unsigned long Address; unsigned long Data; Description: These functions are the MPC860P processor-specific functions that provide interrupt and exce
Monitor: MPC860P-Specific Functions Vector: Cause of Exception: (continued) 0x27 Software Interrupt level 3 0x28 Hardware interrupt level 4 (IRQ4*) 0x29 Software Interrupt level 4 0x2a Hardware interrupt level 5 (IRQ5*) 0x2b Software Interrupt level 5 0x2c Hardware interrupt level 6 (IRQ6*) 0x2d Software Interrupt level 6 0x2e Hardware interrupt level 7 (IRQ7*) 0x2f Software Interrupt level 7 0x30 PCI9060ES LINTO* 0x31 PCI9060ES LSERR* The function VecInit initializes all entries i
Monitor: Standard Monitor Functions Description: The functions UnMaskInts and MaskInts are used to enable and disable external interrupts at the processor. Status getMSR setMSR(Data) clrMSR(Data) getTBU getTBL getDEC getSRR0 getSRR1 getIC_CST getDC_CST getICTRL() writeICTRL() Description: The functions getMSR, setMSR(Data), and clrMSR return the value of the Machine State register (MSR). setMSR and clrMSR either set or clear the bits in the MSR.
Monitor: Standard Monitor Functions unsigned long atoX(p, Base) char *p; int Base; BinToHex(Val) unsigned long Val; HexToBin(Val) unsigned long Val; FindBitSet(Number) unsigned long Number; Description: These functions are a collection of numeric conversion programs used to convert character strings to numeric values, convert hexadecimal to BCD, BCD to hexadecimal, and to search for bit values. The atoh function converts an ASCII string to a hex number.
Monitor: Standard Monitor Functions See also: StartMon.c, NvMonDefs.h, NVTable.c, “Boot Commands” Section . InitFifo InitFifo(FPtr, StartAddr, Length) struct Fifo *FPtr; unsigned char *StartAddr; int Length; ToFifo(FPtr, c) struct Fifo *FPtr; unsigned char c; FromFifo(FPtr, Ptr) struct Fifo *FPtr; unsigned char *Ptr; Description: These functions provide the necessary interface to initialize, read, and write a software FIFO.
Monitor: Standard Monitor Functions Table 8-7: IsLegal Function Types Type: Value: DECIMAL 0x8 Legal Characters: 0-9 HEX 0x4 0 - 9, A - F, a - f UPPER 0x2 A-Z LOWER 0x1 a-z ALPHA 0x3 A - Z, a - z If the character string contains legal characters, this function returns TRUE; otherwise, it returns FALSE.
Monitor: Standard Monitor Functions returning the block specified by Block to the free pool and allocating a new block of size NumBytes, or by determining that the memory block specified by Block is big enough and returning the same block to be reused. The functions Free and CFree return blocks of memory that were requested by Malloc, Calloc, or ReAlloc to the free memory pool.
Monitor: Standard Monitor Functions struct NVExample { NV_Internal Internal; unsigned long XPos, YPos; unsigned short Mag; } NVEx; NVField ExFields[] = { { “XPos”, (char *) &NVEx.XPos, sizeof(NVEx.XPos), NV_TYPE_DECIMAL, 0, 100, NULL}, { “YPos”, (char *) &NVEx.YPos, sizeof(NVEx.YPos), NV_TYPE_DECIMAL, 0, 200, NULL}, { “Depth” (char *) &NVEx.Mag, sizeof(NVEx.
Monitor: Standard Monitor Functions The second parameter, Base, indicates the base address of the data structure to be operated on, and the Size parameter indicates the size of the data structure to be operated on. The Offset parameter specifies the byte offset in the nonvolatile memory device where the data structure is to be stored. An example of how to initialize, store, and recall the example data structure is shown below.
Monitor: Standard Monitor Functions int Baud; baud_d(Baud) int Baud; tx_empty(void) Description: The serial support functions defined here provide the ability to read, write, and poll the monitor’s serial devices. The monitor initializes and controls two serial devices: the console to provide the user interface and the modem (also known as “download” or “remote” device) to connect to a development system.
Monitor: Standard Monitor Functions The function CmpStr compares the two null terminated strings pointed to by Str1 and Str2. If they are equal, it returns TRUE; otherwise, it returns FALSE. Note that this version does not act the same as the UNIX® strcmp function. CmpStr is non-case-sensitive and only matches characters up to the length of Str1. This is useful for pattern matching and other functions. The function StrCmp compares the two null terminated strings pointed to by Str1 and Str2.
Monitor: Standard Monitor Functions The function ByteAddrTest performs a byte-oriented test of the specified memory region. Each location is tested by writing the lowest byte of the location address through the entire memory region and verifying each location. The function WordAddrTest performs a word-oriented test of the specified memory region. Each location is tested by writing the lowest word of the location address through the entire memory region and verifying each location.
Monitor: Standard Monitor Functions If detailed information on the argument formats and argument modifiers is required, see your local C programmer’s manual for details. Not all of the argument formats are supported. The supported formats are %d, %o, %u, %x, %X, %c, and %s.
Section 9 Acronyms ASCII CPU CSA DRAM EC EEPROM EIA EMC ESD ETSI FCC FDL HDLC I2C IEC JTAG LED MAC MDI NVRAM PCB PCI PLD PMC RISC RMA ROM TBD TDM UART UL USB American Standard Code for Information Interchange Central Processing Unit Canadian Standards Association Dynamic Random Access Memory European Community Electrically Erasable Programmable Read-Only Memory Electronic Industries Alliance Electromagnetic Compatibility Electrostatic Discharge European Telecommunications Standards Institute Federal Comm
Acronyms: 9-2 (continued) PmT1 and PmE1 User’s Manual 10002367-02
Index A abbreviations for monitor commands . 8-6, 8-7 acronyms . . . . . . . . . . . . . . . . . . . . 9-1 ADDRESS and DATA signals, PCI . . 7-10 air flow rate . . . . . . . . . . . . . . . . . . . 2-6 ambiguous command, monitor . . 8-29 arithmetic commands . . . . . . . . . 8-27 autoboot cancellation . . . . . . . . . . 8-29 B base address registers, PCI . . 7-2, 7-4, 7-5 baud rate generator control (BRGC) register . . . . . . . . . . . . . . . . . . . . . . 5-6 binary download format . . . . . . . .
Manufacturing . . . . . . . . . . . . . . 8-3 Misc . . . . . . . . . . . . . . . . .8-2, 8-17 H HardwareConfig monitor group . . . 8-3 HDLC . . . . . . . . . . . . . . . . . . . . . . . . 5-4 hex-Intel file example . . . . . . . . . . . . . . . 8-23 records . . . . . . . . . . . . . 8-18, 8-21 I IDMA channels . . . . . . . . . . . . . . . . 5-4 initialization device select signal, PCI . . . . . . 7-10 error, nonvolatile memory . . . . 8-28 of board to defaults . . . . . . . . . 8-31 of CPM registers . . .
Index (continued) getTBU . . . . . . . . . . . . . . . . . . . 8-36 HexToBin . . . . . . . . . . . . . . . . . 8-37 InitBoard . . . . . . . . . . . . . . . . . . 8-31 InitFifo. . . . . . . . . . . . . . . . . . . . 8-38 Interact . . . . . . . . . . . . . . . . . . . 8-44 invalidate_dcache. . . . . . . . . . . 8-33 invalidate_icache . . . . . . . . . . . 8-33 IsLegal . . . . . . . . . . . . . . . . . . . . 8-38 IsPowerUp. . . . . . . . . . . . . . . . . 8-31 KBHit . . . . . . . . . . . . . . . . . . . . .
Index (continued) environmental . . . . . . . . . . . . . . 2-6 mechanical . . . . . . . . . . . . . . . . . 2-1 power . . . . . . . . . . . . . . . . . . . . . 2-6 S-records . . . . . . . . . 8-18, 8-19, 8-24 file example . . . . . . . . . . . . . . . 8-26 start address record . . . . . . . . . . . 8-22 start-up display, monitor . . . . . . . . 8-4 static control . . . . . . . . . . . . . . . . . . 2-1 stop signal, PCI . . . . . . . . . . . . . . . 7-11 string format . . . . . . . . . . . . . .
Notes ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ________________________________________
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