Technical data

ManualsBrandsEmerson ManualsComputer equipmentMVME6100

Embedded Computing for

Business-Critical Continuity

MVME6100 Single Board Computer

Installation and Use

P/N: 6806800D58E

March 2009

Summary of content (118 pages)

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Embedded Computing for Business-Critical ContinuityTM MVME6100 Single Board Computer Installation and Use P/N: 6806800D58E March 2009
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© 2009 Emerson All rights reserved. Trademarks Emerson, Business-Critical Continuity, Emerson Network Power and the Emerson Network Power logo are trademarks and service marks of Emerson Electric Co. © 2008 Emerson Electric Co. All other product or service names are the property of their respective owners. Intel® is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.
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Contents About this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1 Hardware Preparation and Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.1 1.2 1.3 1.4 1.5 1.6 1.7 2 Startup and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.1 2.2 2.
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Contents Contents 3.5 Firmware Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.5.1 Default VME Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.5.2 Control Register/Control Status Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.5.3 Displaying VME Settings . . . . . . . . . . . . . . . . . . .
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Contents 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 5 4.6.9 I2O Message Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.6.10 Four Channel Independent DMA Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.6.11 I2C Serial Interface and Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.6.12 Interrupt Controller . . . . .
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Contents Contents A Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 A.1 A.2 C Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 C.1 C.2 C.3 B Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 A.
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List of Tables Table 1-1 Table 1-2 Table 1-3 Table 1-4 Table 1-5 Table 2-1 Table 3-1 Table 3-2 Table 4-1 Table 4-2 Table 5-1 Table 5-2 Table 5-3 Table 5-4 Table 5-5 Table 5-6 Table 5-7 Table 5-8 Table 5-9 Table 5-10 Table 5-11 Table 5-12 Table 5-13 Table 5-14 Table 5-15 Table 5-16 Table 5-17 Table 5-18 Table 5-19 Table 5-20 Table 5-21 Table A-1 Table A-2 Table C-1 Table C-2 Table C-3 Startup Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Tables Table B-1 8 Thermally Significant Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Figures Figure 1-1 Figure 1-2 Figure 1-3 Figure 1-4 Figure 4-1 Figure B-1 Figure B-2 Figure B-3 Figure B-4 Component Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SCON Header Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PMC/IPMC Header Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Figures 10 MVME6100 Single Board Computer Installation and Use (6806800D58E)
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About this Manual Overview of Contents This manual is divided into the following chapters and appendices: Chapter 1, Hardware Preparation and Installation, provides MVME6100 board preparation and installation instructions, as well as ESD precautionary notes. Chapter 2, Startup and Operation, provides the power-up procedure and identifies the switches and indicators on the MVMEM6100. Chapter 3, MOTLoad Firmware, describes the basic features of the MOTLoad firmware product.
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About this Manual About this Manual As of the printing date of this manual, the MVME61006E supports the models listed below. Model Number Description MVME61006E-0161 1.267 GHz MPC7457 processor, 512MB DDR memory, 128MB Flash, Scanbe handles MVME61006E-0163 1.267 GHz MPC7457 processor, 512MB DDR memory,128MB Flash, IEEE handles MVME61006E-0171 1.267 GHz MPC7457 processor, 1GB DDR memory, 128MB Flash, Scanbe handles MVME61006E-0173 1.
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About this Manual Notation Description [text] Notation for software buttons to click on the screen and parameter description ... Repeated item for example node 1, node 2, ..., node 12 . Omission of information from example/command that is not necessary at the time being . . .. Ranges, for example: 0..
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About this Manual About this Manual Summary of Changes This is the third edition of the Installation and Use manual. It supersedes the November 2007 edition and incorporates the following changes. Part Number Date Changes 6806800D58E March 2009 Added csUserAltBoot command to Table "MOTLoad Commands" on page 33 , editorial changes 6806800D58D April 2008 Updated to Emerson publications style. 6806800D58C January 2008 Updated to remove two incorrect sources of reset.
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Chapter 1 Hardware Preparation and Installation 1.1 Overview This chapter contains the following information: 1.2 z Board preparation and installation instructions z ESD precautionary notes Description The MVME6100 is a single-slot, single-board computer based on the MPC7457 processor, the MV64360 system controller, the Tsi148 VME Bridge ASIC, up to 1 GB of ECC-protected DDR DRAM, up to 128MB of flash memory, and a dual Gigabit Ethernet interface.
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Hardware Preparation and Installation The MVME6100 board interfaces to the VMEbus via the P1 and P2 connectors, which use 5-row 160-pin connectors as specified in the VME64 Extension Standard. It also draws +12V and +5V power from the VMEbus backplane through these two connectors. The +3.3V, +2.5V, +1.8V, and processor core supplies are regulated on-board from the +5V power. For maximum VMEbus performance, the MVME6100 should be mounted in a VME64x compatible backplane (5-row).
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Hardware Preparation and Installation 1.3.1 Overview of Startup Procedures The following table lists the things you will need to do before you can use this board and tells where to find the information you need to perform each step. Be sure to read this entire chapter, including all Caution and Warning notes, before you begin. Table 1-1 Startup Overview 1.3.2 What you need to do... Refer to... Unpack the hardware.
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Hardware Preparation and Installation If the shipping carton is damaged upon receipt, request that the carrier’s agent be present during the unpacking and inspection of the equipment. Avoid touching areas of integrated circuitry; static discharge can damage circuits. Emerson strongly recommends that you use an antistatic wrist strap and a conductive foam pad when installing or upgrading a system.
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Hardware Preparation and Installation Jumpers/switches are used to control those options that are not software configurable. These jumper settings are described further on in this section. If you are resetting the board jumpers from their default settings, it is important to verify that all settings are reset properly. Figure 1-1 illustrates the placement of the jumpers, headers, connectors, switches, and various other components on the MVME6100.
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Hardware Preparation and Installation The MVME6100 is factory tested and shipped with the configuration described in the following sections.
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Hardware Preparation and Installation 1.4.1 SCON Header (J7) A 3-pin planar header allows the choice for auto/enable/disable SCON VME configuration. A jumper installed across pins 1 and 2 configures for SCON always enabled. A jumper installed across pins 2 and 3 configures for SCON disabled. No jumper installed configures for auto SCON. Figure 1-2 SCON Header Settings J7 J7 1 1 1 2 2 2 3 3 3 Auto-SCON (factory configuration) 1.4.
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Hardware Preparation and Installation A jumper installed across pins 1 and 2 on all nine headers selects PMC1 for PMC I/O mode. A jumper across pins 2 and 3 on all nine headers selects IPMC I/O mode. Figure 1-3 PMC/IPMC Header Settings IPMC P2 I/O for IPMC Mode (factory configuration) J10 J16 J15 J17 J18 J25 J26 J27 J28 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 PMC1 P2 I/O for PMC Mode J10 1.4.
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Hardware Preparation and Installation (or to exclude incompatible PMC cards). In the default position in the middle of the four PMC site connectors, the signaling voltage for the PMC sites is set to 5.0V. When the keying pins are moved to the alternate location in front of their set of four PMC connectors, the signaling voltage for the PMC sites is set for 3.3V. The keying pins for both PMC sites must be set to the same signaling voltage.
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Hardware Preparation and Installation The following illustration shows jumper setting options for J30.
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Hardware Preparation and Installation The SROM WP switch is OFF to enable write protection on all I2C. The switch is ON to disable the I2C EEPROM write protection. Table 1-3 SROM Configuration Switch (S3) Position 2 1 FUNCTION SROM WP SROM_INIT DEFAULT (OFF) WP No SROM_INIT S3 position 3-8 defines the VME Geographical Address if the MVME6100 is installed in a 3-row backplane.
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Hardware Preparation and Installation 1.4.6 Flash Boot Bank Select Configuration Switch (S4) A 4-position SMT configuration switch is located on the board to control Flash Bank B Boot block write-protect and Flash Bank A write-protect. Select the Flash Boot bank and the programmed/safe start ENV settings. It is recommended that Bank B Write Protect always be enabled. The Bank B Boot WP switch is OFF to indicate that the Flash Bank B Boot block is writeprotected.
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Hardware Preparation and Installation 1.5 Installing the Blade Procedure Use the following steps to install the MVME6100 into your computer chassis. 1. Attach an ESD strap to your wrist. Attach the other end of the ESD strap to an electrical ground (refer to Unpacking Guidelines). The ESD strap must be secured to your wrist and to ground throughout the procedure. 2. Remove any filler panel that might fill that slot. 3. Install the top and bottom edge of the MVME6100 into the guides of the chassis.
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Hardware Preparation and Installation Figure 1-1 on page 20 shows the locations of the various connectors while Table 1-5 lists them for you. Refer to Chapter 5, Pin Assignments for the pin assignments of the connectors listed below. Table 1-5 MVME6100 Connectors 1.
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Chapter 2 Startup and Operation 2.1 Introduction This chapter gives you information about the: 2.2 z Power-up procedure z Switches and indicators Applying Power After you verify that all necessary hardware preparation is complete and all connections are made correctly, you can apply power to the system. When you are ready to apply power to the MVME6100: 2.
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Startup and Operation The following table describes these indicators: Table 2-1 Front-Panel LED Status Indicators 30 Function Label Color Description CPU Bus Activity CPU Green CPU bus is busy Board Fail BDFAIL Yellow Board has a failure MVME6100 Single Board Computer Installation and Use (6806800D58E)
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Chapter 3 MOTLoad Firmware 3.1 Overview The MOTLoad firmware package serves as a board power-up and initialization package, as well as a vehicle from which user applications can be booted. A secondary function of the MOTLoad firmware is to serve in some respects as a test suite providing individual tests for certain devices. This chapter includes a list of standard MOTLoad commands, the default VME and firmware settings that are changeable by the user, remote start, and the alternate boot procedure.
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MOTLoad Firmware Operationally, MOTLoad utility applications differ from MOTLoad test applications in several ways: 3.3.2 z Only one utility application operates at any given time (that is, multiple utility applications cannot be executing concurrently) z Utility applications may interact with the user. Most test applications do not. Tests A MOTLoad test application determines whether or not the hardware meets a given standard. Test applications are validation tests.
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MOTLoad Firmware Most MOTLoad tests can be organized to execute as a group of related tests (a testSuite) through the use of the testSuite command. The expert operator can customize their testing by defining and creating a custom testSuite(s). The list of built-in and user-defined MOTLoad testSuites, and their test contents, can be obtained by entering testSuite -d at the MOTLoad prompt. All testSuites that are included as part of a product specific MOTLoad firmware package are product specific.
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MOTLoad Firmware Table 3-1 MOTLoad Commands (continued) Command Description blkVe Block Verify blkWr Block Write bmb Block Move Byte/Halfword/Word bmh bmw br Assign/Delete/Display User-Program Break-Points bsb Block Search Byte/Halfword/Word bsh bsw bvb Block Verify Byte/Halfword/Word bvh bvw cdDir ISO9660 File System Directory Listing cdGet ISO9660 File System File Load clear Clear the Specified Status/History Table(s) cm Turns on Concurrent Mode csb Calculates a Checksum Specified
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MOTLoad Firmware Table 3-1 MOTLoad Commands (continued) Command Description execProgram Execute Program fatDir FAT File System Directory Listing fatGet FAT File System File Load fdShow Display (Show) File Discriptor flashLock Flash Memory Sector Lock flashProgram Flash Memory Program flashShow Display Flash Memory Device Configuration Data flashUnlock Flash Memory Sector Unlock gd Go Execute User-Program Direct (Ignore Break-Points) gevDelete Global Environment Variable Delete gevDump
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MOTLoad Firmware Table 3-1 MOTLoad Commands (continued) Command Description mmb Memory Modify Bytes/Halfwords/Words mmh mmw 36 mpuFork Execute program from idle processor mpuShow Display multi-processor control structure mpuStart Start the other MPU netBoot Network Boot (BOOT/TFTP) netShow Display Network Interface Configuration Data netShut Disable (Shutdown) Network Interface netStats Display Network Interface Statistics Data noCm Turns off Concurrent Mode pciDataRd Read PCI Device
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MOTLoad Firmware Table 3-1 MOTLoad Commands (continued) Command Description stop Stop Date and Time (Power-Save Mode) taskActive Display the Contents of the Active Task Table tc Trace (Single-Step) User Program td Trace (Single-Step) User Program to Address testDisk Test Disk testEnetPtP Ethernet Point-to-Point testNvramRd NVRAM Read testNvramRdWr NVRAM Read/Write (Destructive) testRam RAM Test (Directory) testRamAddr RAM Addressing testRamAlt RAM Alternating testRamBitToggle RAM B
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MOTLoad Firmware Table 3-1 MOTLoad Commands (continued) 3.
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MOTLoad Firmware MVME6100> If an invalid MOTLoad command is entered at the MOTLoad command line prompt, MOTLoad displays a message that the command was not found. Example: MVME6100> mytest "mytest" not found MVME6100> If the user enters a partial MOTLoad command string that can be resolved to a unique valid MOTLoad command and presses the carriage-return key, the command will be executed as if the entire command string had been entered.
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MOTLoad Firmware 3.4.
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MOTLoad Firmware Usage: testRam [-aPh] [-bPh] [-iPd] [-nPh] [-tPd] [-v] Description: RAM Test [Directory] Argument/Option Description -a Ph: Address to Start (Default = Dynamic Allocation) -b Ph: Block Size (Default = 16KB) -i Pd: Iterations (Default = 1) -n Ph: Number of Bytes (Default = 1MB) -t Ph: Time Delay Between Blocks in OS Ticks (Default = 1) -v O : Verbose Output MVME6100> 3.
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MOTLoad Firmware The VMEbus Master Control Register is set to the default (RESET) condition. z MVME6100> vmeCfg –s –r238 Displaying the selected Default VME Setting - interpreted as follows: VMEbus Control Register = 00000008 MVME6100> The VMEbus Control Register is set to a Global Timeout of 2048 μseconds.
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MOTLoad Firmware Inbound window 0 (ITAT0) is not enabled; Virtual FIFO at 256 bytes, 2eSST timing at SST320, respond to 2eSST, 2eVME, MBLT, and BLT cycles, A32 address space, respond to Supervisor, User, Program, and Data cycles. Image maps from 0x00000000 to 0x1FFF0000 on the VMbus, translates 1x1 to the PCI-X bus (thus 1x1 to local memory). To enable this window, set bit 31 of ITAT0 to 1.
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MOTLoad Firmware Outbound Image 2 Translation Offset Upper Register = 00000000 Outbound Image 2 Translation Offset Lower Register = 40000000 Outbound Image 2 2eSST Broadcast Select Register = 00000000 MVME6100> Outbound window 2 (OTAT2) is enabled, 2eSST timing at SST320, transfer mode of SCT, A24/D32 Supervisory access.
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MOTLoad Firmware Outbound Image 7 Translation Offset Upper Register = 00000000 Outbound Image 7 Translation Offset Lower Register = 4F000000 Outbound Image 7 2eSST Broadcast Select Register = 00000000 MVME6100> Outbound window 7 (OTAT7) is enabled, 2eSST timing at SST320, transfer mode of SCT, CR/CSR Supervisory access.
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MOTLoad Firmware 3.5.
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MOTLoad Firmware 3.5.5 Deleting VME Settings To delete the changeable VME setting (restore default value), type the following at the firmware prompt: 3.5.
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MOTLoad Firmware 3.6 Remote Start As described in the MOTLoad Firmware Package User's Manual, listed in Appendix C, Related Documentation, remote start allows the user to obtain information about the target board, download code and/or data, modify memory on the target, and execute a downloaded program. These transactions occur across the VMEbus in the case of the MVME6100.
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MOTLoad Firmware Mailbox 0 is at offset 7f348 in the CR/CSR space Mailbox 1 is at offset 7f34C in the CR/CSR space Mailbox 2 is at offset 7f350 in the CR/CSR space Mailbox 3 is at offset 7f354 in the CR/CSR space The selection of the mailbox used by remote start on an individual MVME6100 is determined by the setting of a global environment variable (GEV). The default mailbox is zero. Another GEV controls whether remote start is enabled (default) or disabled.
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MOTLoad Firmware z If a valid USER boot image is not found, search the active flash bank, possibly interactively, for a valid MCG boot image; anticipated to be upgrade of MCG firmware. If found, the image is executed. A return to the boot block code is not anticipated.
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MOTLoad Firmware The scan is performed downwards from boot block image and searches first for POST, then USER, and finally MCG images. In the case of multiple images of the same type, control is passed to the first image encountered in the scan. Safe Start, whether invoked by hitting ESC on the console within the first five seconds following power-on reset or by setting the Safe Start jumper, interrupts the scan process. The user may then display the available boot images and select the desired image.
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MOTLoad Firmware 3.10 Boot Images Valid boot images whether POST, USER, or MCG, are located on 1MB boundaries within flash. The image may exceed 1MB in size. An image is determined valid through the presence of two "valid image keys" and other sanity checks.
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MOTLoad Firmware startPtr++; } return(checksum); } 3.10.2 Image Flags The image flags of the header define various bit options that control how the image will be executed.
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MOTLoad Firmware z DONT_AUTO_RUN If set, this flag indicates that the image is not to be selected for automatic execution. A user, through the interactive command facility, may specify the image to be executed. MOTLoad currently uses an Image Flag value of 0x3, which identifies itself as an Alternate MOTLoad image that executes from RAM. MOTLoad currently does not support execution from flash. 3.10.3 User Images These images are user-developer boot code; for example, a VxWorks bootrom image.
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MOTLoad Firmware 3.10.4 Alternate Boot Data Structure The globalData field of the alternate boot data structure points to an area of RAM which was initialized to zeroes by the boot loader. This area of RAM is not cleared by the boot loader after execution of a POST image, or other alternate boot image, is executed. It is intended to provide a user a mechanism to pass POST image results to subsequent boot images.
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MOTLoad Firmware 3.10.6 Boot Image Firmware Scan The scan is performed by examining each 1 MB boundary for a defined set of flags that identify the image as being POST, USER, or Alternate MOTLoad. POST is a user-developed Power On Self Test that would perform a set of diagnostics and then return to the boot loader image. USER would be a boot image, such as the VxWorks bootrom, which would perform board initialization. A bootable VxWorks kernel would also be a USER image.
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MOTLoad Firmware 'h':this help screen boot> d Addr FFE00000 Size 00100000 Flags 00000003 Name: MOTLoad Addr FFD00000 Size 00100000 Flags 00000003 Name: MOTLoad boot> c NOPQRSTUVabcdefghijk#lmn3opqrsstuvxyzaWXZ Copyright Motorola Inc. 1999-2004, All Rights Reserved MOTLoad RTOS Version 2.0, PAL Version 0.b EA02 ... MVME6100> 3.
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MOTLoad Firmware 58 MVME6100 Single Board Computer Installation and Use (6806800D58E)
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Chapter 4 Functional Description 4.1 Overview This chapter describes the MVME6100 on a block diagram level. 4.2 Features The following table lists the features of the MVME6100. Table 4-1 MVME6100 Features Summary Feature Description Processor — Single 1.
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Functional Description Table 4-1 MVME6100 Features Summary (continued) Feature Description On-board Peripheral Support — Dual 10/100/1000 Ethernet ports routed to front panel RJ-45 connectors, one optionally routed to P2 backplane — Two asynchronous serial ports provided by an ST16C554D; one serial port is routed to a front panel RJ-45 connector and the second serial port is routed to an on-board header (J29, as factory default build configuration).
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Functional Description 4.3 Block Diagram Figure 4-1 shows a block diagram of the overall board architecture. Figure 4-1 MVME6100 Block Diagram L3 Cache 2MB DDR RAM 512MB-1GB Soldered Flash Bank A 64MB 211 MHz DDR DDR RAM 512MB-1GB MPC7457 1.
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Functional Description 4.5 L3 Cache The MVME6100 external L3 cache is implemented using two 8Mb DDR SRAM devices. The L3 cache bus is 72-bits wide (64 bits of data and 8 bits of parity) and operates at 211 MHz. The L3 cache interface is implemented with an on-chip, 8-way, set-associative tag memory. The external SRAMs are accessed through a dedicated L3 cache port that supports one bank of SRAM. The L3 cache normally operates in copyback mode and supports system cache coherency through snooping.
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Functional Description All of the above interfaces are connected through a cross bar fabric. The cross bar enables concurrent transactions between units. For example, the cross bar can simultaneously control: 4.6.1 z A Gigabit Ethernet MAC fetching a descriptor from the integrated SRAM z The CPU reading from the DRAM z The DMA moving data from the device bus to the PCI bus CPU Bus Interface The CPU interface (master and slave) operates at 133 MHz and +2.5V signal levels using MPX bus modes.
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Functional Description The SDRAM controller supports a wide range of SDRAM timing parameters. These parameters can be configured through the SDRAM Mode register and the SDRAM Timing Parameters register. Refer to the MV64360 Data Sheet, listed in Appendix C, Related Documentation, for additional information and programming details. The DRAM controller contains four transaction queues–two write buffers and two read buffers.
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Functional Description PCI bus 0 is connected to the Tsi148 device and PMCspan bridge. PCI bus 0 is configured for 133 MHz PCI-X mode. The MV64360 PCI interfaces are fully PCI rev. 2.2 and PCI-X rev 1.0 compliant and support both address and data parity checking. The MV64360 contains all of the required PCI configuration registers. All internal registers, including the PCI configuration registers, are accessible from the CPU bus or the PCI buses. 4.6.
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Functional Description 4.6.8 Watchdog Timer The MV64360 internal watchdog timer is a 32-bit count-down counter that can be used to generate a non-maskable interrupt or reset the system in the event of unpredictable software behavior. After the watchdog timer is enabled, it becomes a free running counter that must be serviced periodically to keep it from expiring. Refer to the MV64360 Data Sheet, listed in Appendix C, Related Documentation, for additional information and programming details. 4.6.
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Functional Description The MVME6100 board contains the following I2C serial devices: z 8KB EEPROM for user-defined MV64360 initialization z 8KB EEPROM for VPD z 8KB EEPROM for user data z Two 256 byte EEPROMs for SPD z DS1621 temperature sensor z One 256 byte EEPROM for PMCspan PCIx-PCIx bridge use The 8KB EEPROM devices are implemented using Atmel AT24C64A devices or similar parts. These devices use two byte addressing to address the 8KB of the device. 4.6.
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Functional Description 4.6.13 PCI Bus Arbitration PCI arbitration is performed by the MV64360 system controller. The MV64360 integrates two PCI arbiters, one for each PCI interface (PCI bus 0/1). Each arbiter can handle up to six external agents plus one internal agent (PCI bus 0/1 master). The internal PCI arbiter REQ#/GNT# signals are multiplexed on the MV64360 MPP pins. The internal PCI arbiter is disabled by default (the MPP pins function as general-purpose inputs).
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Functional Description 4.10 System Memory MVME6100 system memory consists of double-data-rate SDRAMs. The DDR SDRAMs support two data transfers per clock cycle. The memory device is a standard monolithic (32M x 8 or 64M x 8) DDR, 8-bit wide, 66-pin, TSSOPII package. Both banks are provided on board the MVME6100 and operate at 133 MHz clock frequency with both banks populated. 4.
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Functional Description PMC slot 2 supports: Mezzanine Type: PMC = PCI Mezzanine Card Mezzanine Size: S1B = Single width and standard depth (75mm x 150mm) with front panel PMC Connectors: J21, J22, J23, and J24 (32/64-bit PCI with front and rear I/O) Signalling Voltage: VIO = +3.3V (+5V tolerant) or +5V, selected by keying pin You cannot use 3.3V and 5.0V PMCs together; the voltage keying pin on slots 1 and 2 must be identical. When in 5.0V mode, the bus runs at 33 MHz.
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Functional Description 4.13 Real-Time Clock/NVRAM/Watchdog Timer The real-time clock/NVRAM/watchdog timer is implemented using an integrated SGSThompson M48T37V Timekeeper SRAM and Snaphat battery. The minimum M48T37V watchdog timer time-out resolution is 62.5 msec (1/16s) and maximum time-out period is 124 seconds. The interface for the Timekeeper and SRAM is connected to the MV64360 device controller bus on the MVME6100 board.
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Functional Description 4.17 Processor JTAG/COP Headers The MVME6100 provides JTAG/COP connectors for JTAG/COP emulator support (RISCWatch COP J42), as well as supporting board boundary scan capabilities (Boundary Scan header J8).
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Chapter 5 Pin Assignments 5.1 Overview This chapter provides pin assignments for various headers and connectors on the MMVE6100 single-board computer. z The following tables provide a brief description of the connector, the pin assignments, and signal descriptions for standard and nonstandard connectors on the MVME6100.
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Pin Assignments 5.2.1 PMC Expansion Connector (J4) One 114-pin Mictor connector with a center row of power and ground pins is used to provide PCI expansion capability. The pin assignments for this connector are as follows: Table 5-1 PMC Expansion Connector (J4) Pin Assignments 74 Pin Signal Signal Pin 1 +3.3V +3.
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Pin Assignments Table 5-1 PMC Expansion Connector (J4) Pin Assignments (continued) Pin Signal Signal Pin 39 PAR PCIRST# 40 41 C/BE1# C/BE0# 42 43 C/BE3# C/BE2# 44 45 AD1 AD0 46 47 AD3 AD2 48 49 AD5 AD4 50 51 AD7 AD6 52 53 AD9 AD8 54 55 AD11 AD10 56 57 AD13 AD12 58 59 AD15 AD14 60 61 AD17 AD16 62 63 AD19 AD18 64 65 AD21 AD20 66 67 AD23 AD22 68 69 AD25 AD24 70 71 AD27 AD26 72 73 AD29 AD28 74 75 AD31 AD30 76 +5V MVME6100 Single B
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Pin Assignments Table 5-1 PMC Expansion Connector (J4) Pin Assignments (continued) Pin Signal Signal Pin 77 PAR64 Reserved 78 79 C/BE5# C/BE4# 80 81 C/BE7# C/BE6# 82 83 AD33 AD32 84 85 AD35 AD34 86 87 AD37 AD36 88 89 AD39 AD38 90 91 AD41 AD40 92 93 AD43 AD42 94 95 AD45 AD44 96 97 AD47 AD46 98 99 AD49 AD48 100 101 AD51 AD50 102 103 AD53 AD52 104 105 AD55 AD54 106 107 AD57 AD56 108 109 AD59 AD58 110 111 AD61 AD60 112 113 AD63 AD62
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Pin Assignments 5.2.2 Gigabit Ethernet Connectors (J9, J93) Access to the dual Gigabit Ethernet is provided by two transpower RJ-45 connectors with integrated magnetics and LEDs located on the front panel of the MVME6100. The pin assignments for these connectors are as follows: Table 5-2 Gigabit Ethernet Connectors (J9, J93) Pin Assignment Pin # Signal 1000 Mb/s 10/100 Mb/s 1 CT_BOARD +2.5V +2.
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Pin Assignments The pin assignments for these connectors are as follows. Table 5-3 PMC Slot 1 Connector (J11) Pin Assignments 78 Pin Signal Signal Pin 1 TCK -12V 2 3 GND INTA# 4 5 INTB# INTC# 6 7 PMCPRSNT1# +5V 8 9 INTD# PCI_RSVD 10 11 GND +3.3Vaux 12 13 CLK GND 14 15 GND PMCGNT1# 16 17 PMCREQ1# +5V 18 19 +3.3V (VIO) AD31 20 21 AD28 AD27 22 23 AD25 GND 24 25 GND C/BE3# 26 27 AD22 AD21 28 29 AD19 +5V 30 31 +3.
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Pin Assignments Table 5-3 PMC Slot 1 Connector (J11) Pin Assignments (continued) Pin Signal Signal Pin 51 GND C/BE0# 52 53 AD06 AD05 54 55 AD04 GND 56 57 +3.3V (VIO) AD03 58 59 AD02 AD01 60 61 AD00 +5V 62 63 GND REQ64# 64 Table 5-4 PMC Slot 1 Connector (J12) Pin Assignments Pin Signal Signal Pin 1 +12V TRST# 2 3 TMS TDO 4 5 TDI GND 6 7 GND Not Used 8 9 Not Used Not Used 10 11 Pull-up +3.3V 12 13 RST# Pull-down 14 15 +3.
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Pin Assignments Table 5-4 PMC Slot 1 Connector (J12) Pin Assignments (continued) Pin Signal Signal Pin 35 TRDY# +3.3V 36 37 GND STOP# 38 39 PERR# GND 40 41 +3.3V SERR# 42 43 C/BE1# GND 44 45 AD14 AD13 46 47 M66EN AD10 48 49 AD08 +3.3V 50 51 AD07 REQ1B# 52 53 +3.3V GNT1B# 54 55 Not Used GND 56 57 Not Used EREADY0 58 59 GND Not Used 60 61 ACK64# +3.
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Pin Assignments Table 5-5 PMC Slot 1 Connector (J13) Pin Assignments (continued) Pin Signal Signal Pin 19 AD57 GND 20 21 +3.3V (VIO) AD56 22 23 AD55 AD54 24 25 AD53 GND 26 27 GND AD52 28 29 AD51 AD50 30 31 AD49 GND 32 33 GND AD48 34 35 AD47 AD46 36 37 AD45 GND 38 39 +3.3V (VIO) AD44 40 41 AD43 AD42 42 43 AD41 GND 44 45 GND AD40 46 47 AD39 AD38 48 49 AD37 GND 50 51 GND AD36 52 53 AD35 AD34 54 55 AD33 GND 56 57 +3.
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Pin Assignments Table 5-6 PMC Slot 1 Connector (J14) Pin Assignments (continued) 82 Pin Signal Signal Pin 3 PMC0_3 (P2-C2) PMC0_4 (P2-A2) 4 5 PMC0_5 (P2-C3) PMC0_6 (P2-A3) 6 7 PMC0_7 (P2-C4) PMC0_8 (P2-A4) 8 9 PMC1 _9 (P2-C5) PMC0_10 (P2-A5) 10 11 PMC0_11 (P2-C6) PMC0_12 (P2-A6) 12 13 PMC0_13 (P2-C7) PMC0_14 (P2-A7) 14 15 PMC0_15 (P2-C8) PMC0_16 (P2-A8) 16 17 PMC0_17 (P2-C9) PMC0_18 (P2-A9) 18 19 PMC0_19 (P2-C10) PMC0_20 (P2-A10) 20 21 PMC0_21 (P2-C11) PMC0_22 (P
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Pin Assignments Table 5-6 PMC Slot 1 Connector (J14) Pin Assignments (continued) Pin Signal Signal Pin 57 PMC0_57 (P2-C29) PMC0_58 (P2-A29) 58 59 PMC0_59 (P2-C30) PMC0_60 (P2-A30) 60 61 PMC0_61 (P2-C31) PMC0_62 (P2-A31) 62 63 PMC0_63 (P2-C32) PMC0_64 (P2-A32) 64 Table 5-7 PMC Slot 2 Connector (J21) Pin Assignments Pin Signal Signal Pin 1 TCK -12V 2 3 GND INTC# 4 5 INTD# INTA# 6 7 PMCPRSNT1# +5V 8 9 INTB# PCI_RSVD 10 11 GND +3.
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Pin Assignments Table 5-7 PMC Slot 2 Connector (J21) Pin Assignments (continued) Pin Signal Signal Pin 41 PCI_RSVD PCI_RSVD 42 43 PAR GND 44 45 +3.3V (VIO) AD15 46 47 AD12 AD11 48 49 AD09 +5V 50 51 GND C/BE0# 52 53 AD06 AD05 54 55 AD04 GND 56 57 +3.
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Pin Assignments Table 5-8 PMC Slot 2 Connector (J22) Pin Assignments (continued) Pin Signal Signal Pin 25 IDSEL1 AD23 26 27 +3.3V AD20 28 29 AD18 GND 30 31 AD16 C/BE2# 32 33 GND IDSEL1B 34 35 TRDY# +3.3V 36 37 GND STOP# 38 39 PERR# GND 40 41 +3.3V SERR# 42 43 C/BE1# GND 44 45 AD14 AD13 46 47 M66EN AD10 48 49 AD08 +3.3V 50 51 AD07 REQ1B# 52 53 +3.
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Pin Assignments Table 5-9 PMC Slot 2 Connector (J23) Pin Assignments (continued) 86 Pin Signal Signal Pin 9 +3.3V (VIO) PAR64 10 11 AD63 AD62 12 13 AD61 GND 14 15 GND AD60 16 17 AD59 AD58 18 19 AD57 GND 20 21 +3.3V (VIO) AD56 22 23 AD55 AD54 24 25 AD53 GND 26 27 GND AD52 28 29 AD51 AD50 30 31 AD49 GND 32 33 GND AD48 34 35 AD47 AD46 36 37 AD45 GND 38 39 +3.
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Pin Assignments Table 5-9 PMC Slot 2 Connector (J23) Pin Assignments (continued) Pin Signal Signal Pin 63 GND Reserved 64 Table 5-10 PMC Slot 2 Connector (J24) Pin Assignments Pin Signal Signal Pin 1 PMC1_1 (P2-D1) PMC1_2 (P2-Z1) 2 3 PMC1_3 (P2-D2) PMC1_4 (P2-D3) 4 5 PMC1_5 (P2-Z3) PMC1_6 (P2-D4) 6 7 PMC1_7 (P2-D5) PMC1_8 (P2-Z5) 8 9 PMC1_9 (P2-D6) PMC1_10 (P2-D7) 10 11 PMC1_11 (P2-Z7) PMC1_12 (P2-D8) 12 13 PMC1_13 (P2-D9) PMC1_14 (P2-Z9) 14 15 PMC1_15 (P2-D10 PMC1
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Pin Assignments Table 5-10 PMC Slot 2 Connector (J24) Pin Assignments (continued) 5.2.
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Pin Assignments 5.2.5 VMEbus P1 Connector The VME P1 connector is an 160-pin DIN. The P1 connector provides power and VME signals for 24-bit address and 16-bit data.
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Pin Assignments Table 5-12 VMEbus P1 Connector Pin Assignments (continued) 5.2.
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Pin Assignments Table 5-13 VMEbus P2 Connector Pin Assignments (PMC Mode) (continued) ROW Z ROW A ROW B ROW C ROW D 5 PMC1_8 (J24-8) PMC0_1 0 (J1410) VA25 PMC0_9 (J14-9) PMC1_7 (J24-7) 5 6 GND PMC0_1 2 (J1412) VA26 PMC0_11 (J14-11) PMC1_9 (J24-9) 6 7 PMC1_11 (J24-11) PMC0_1 4 (J1414) VA27 PMC0_13 (J14-13) PMC1_10 (J24-10) 7 8 GND PMC0_1 6 (J1416) VA28 PMC0_15 (J14-15) PMC1_12 (J24-12) 8 9 PMC1_14 (J24-14) PMC0_1 8 (J1418) VA29 PMC0_17 (J14-17) PMC1_13 (J24-13) 9 10
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Pin Assignments Table 5-13 VMEbus P2 Connector Pin Assignments (PMC Mode) (continued) 92 ROW Z ROW A ROW B ROW C ROW D 17 PMC1_26 (J24-J26) PMC0_3 4 (J1434) VD19 PMC0_33 (J14-33) PMC1_25 (J24-25) 17 18 GND PMC0_3 6 (J1436) VD20 PMC0_35 (J14-35) PMC1_27 (J24-27) 18 19 PMC1_29 (J24-29) PMC0_3 8 (J1438) VD21 PMC0_37 (J14-37) PMC1_28 (J24-28) 19 20 GND PMC0_4 0 (J1440) VD22 PMC0_39 (J14-39) PMC1_30 (J24-30) 20 21 PMC1_32 (J24-32) PMC0_4 2 (J1442) VD23 PMC0_41 (J14-41) PM
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Pin Assignments Table 5-13 VMEbus P2 Connector Pin Assignments (PMC Mode) (continued) ROW Z ROW A ROW B ROW C ROW D 28 GND PMC0_5 6 (J1456) VD29 PMC0_55 (J14-55)/RXB PMC1_42 (J24-42) 28 29 PMC1_44 (J30 D9C9) or P2_IO_GLAN1_M DIO_3- (J30 B9-C9) PMC0_5 8 (J1458) VD30 PMC0_57 (J14-57)/RTSB PMC1_43 (J24-43) 29 30 GND PMC0_6 0 (J14-60) VD31 PMC0_59 (J14-59)/CTSB PMC1_45 (J24-45) 30 31 PMC1_46 (J30 D10-C10) or P2_IO_GLAN1_M DIO_3+ (J30 B10C10) PMC0_6 2 (J1462) GND PMC0_61 (J14-61)
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Pin Assignments Table 5-14 VME P2 Connector Pinouts with IPMC712 (continued) 94 Pin Row Z Row A Row B Row C Row D 5 PMC2_8 DB4# VA25 NOT USED PMC2_7 (J24-7) 6 GND DB5# VA26 NOT USED PMC2_9 (J24-9) 7 PMC2_11 DB6# VA27 +12V (LAN) PMC2_10 (J24-10) 8 GND DB7# VA28 PRSTB# PMC2_12 (J24-12) 9 PMC2-14 DBP# VA29 P DB0 PMC2_13 (J24-13) 10 GND ATN# VA30 P DB1 PMC2_15 (J24-15) 11 PMC2_17 BSY# VA31 P DB2 PMC2_16 (J24-16) 12 GND ACK# GND P DB3 PMC2_18 (J24-18) 13
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Pin Assignments Table 5-14 VME P2 Connector Pinouts with IPMC712 (continued) Pin Row Z Row A Row B Row C Row D 32 GND RTXC4 +5V DCD2 VPC Table 5-15 VME P2 Connector Pinouts with IPMC761 Pin Row Z Row A Row B Row C Row D 1 DB8# DB0# +5V RD- (10/100) PMC2_1 (J24-1) 2 GND DB1# GND RD+ (10/100) PMC2_3 (J24-3) 3 DB9# DB2# RETRY# TD- (10/100) PMC2_4 (J24-4) 4 GND DB3# VA24 TD+ (10/100) PMC2_6 (J24-6) 5 DB10# DB4# VA25 Not Used PMC2_7 (J24-7) 6 GND DB5# VA26 Not
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Pin Assignments Table 5-15 VME P2 Connector Pinouts with IPMC761 (continued) Pin Row Z Row A Row B Row C Row D 23 PMC2_35 (J24-35) RTXC3 VD24 TXD1_232 PMC2_34 (J24-34) 24 GND TRXC3 VD25 RXD1_232 PMC2_36 (J24-36) 25 PMC2_38 (J24-38) TXD4 VD26 RTS1_232 PMC2_37 (J24-37) 26 GND RXD4 VD27 CTS1_232 PMC2_39 (J24-39) 27 PMC2_41 (J24-41) RTXC4 VD28 TXD2_232 PMC2_40 (J24-40) 28 GND TRXC4 VD29 RXD2_232 PMC2_42 (J24-42) 29 PMC2_44 (J24-44) VD30 RTS2_232 PMC2_43 (J24-43) 3
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Pin Assignments 5.3.1 SCON Header (J7) A 3-pin planar header allows the choice for auto/enable/disable SCON VME configuration. A jumper installed across pins 1 and 2 configures for SCON always enabled. A jumper installed across pins 2 and 3 configures for SCON disabled. No jumper installed configures for auto SCON. The pin assignments for this connector are as follows: Table 5-16 SCON Header (J7) Pin Assignments 5.3.
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Pin Assignments 5.3.3 PMC/IPMC Selection Headers (J10, J15 — J18, J25 — J28) Nine 3-pin 2 mm planar headers allow for PMC/IPMC I/O selection. These nine headers can also be combined into one single header block where a block shunt can be used as a jumper.
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Pin Assignments Table 5-19 COM2 Planar Serial Port Header (J29) Pin Assignments (continued) 5.3.
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Pin Assignments 5.3.6 Processor JTAG/COP Header (J42) There is one standard 16-pin header that provides an interface for the RISCWatch function.
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Appendix A A Specifications A.1 Power Requirements In its standard configuration, the MVME6100 requires +5 V, +12 V, and —12 V for operation. On-board converters supply the processor core voltage, +3.3 V, +1.8 V, and +2.5 V. A.1.1 Supply Current Requirements Table A-1 provides an estimate of the typical and maximum current required from each of the input supply voltages.
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Specifications Table A-2 MVME6100 Specifications (continued) 102 Characteristics Specifications Physical Dimensions 6U, 4HP wide (233 mm x 160 mm x 20 mm) (9.2 in. x 6.3 in. x 0.8 in) MTBF 328,698 hours, calculated based on BellCore Issue 6, Method 1, case 3 for the central office or environmentally controlled remote shelters or customer premise areas.
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Appendix C Related Documentation C C.1 Emerson Network Power - Embedded Computing Documents The Emerson Network Power - Embedded Computing publications listed below are referenced in this manual. You can obtain electronic copies of Emerson Network Power - Embedded Computing publications by contacting your local Emerson sales office. For documentation of final released (GA) products, you can also visit the following website: http://www.emersonnetworkpowerembeddedcomputing.
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Related Documentation Table C-2 Manufacturers’ Documents (continued) Document Title and Source Publication Number PowerPC™ Apollo Microprocessor Implementation Definition Book IV Web Site: http://www.freescale.com Addendum to SC-Vger Book IV Version - 1.0 04/21/00 MV64360 System Controller for PowerPC Processors Data Sheet MV-S100414-00C Marvell Technologies, Ltd. Web Site: http://www.marvell.
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Related Documentation Table C-2 Manufacturers’ Documents (continued) Document Title and Source Publication Number 2-Wire Serial CMOS EEPROM AT24C02N AT24C64A Atmel Corporation San Jose, CA Web Site: http://www.atmel.com Dallas Semiconductor DS1621Digital Thermometer and Thermostat DS1621 Dallas Semiconductor Web Site: http://www.dalsemi.com TSOP Type I Shielded Metal Cover SMT Yamaichi Electronics USA Web Site: http://www.yeu.com C.
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Related Documentation Table C-3 Related Specifications (continued) Document Title and Source Publication Number IEEE - PCI Mezzanine Card Specification (PMC) P1386.1 Draft 2.0 Institute of Electrical and Electronics Engineers, Inc.
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Appendix B B Thermal Validation B.1 Overview Board component temperatures are affected by ambient temperature, air flow, board electrical operation, and software operation. In order to evaluate the thermal performance of a circuit board assembly, it is necessary to test the board under actual operating conditions. These operating conditions vary depending on system design.
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Thermal Validation The preferred measurement location for a component may be junction, case, or air as specified in the table. Junction temperature refers to the temperature measured by an on-chip thermal device. Case temperature refers to the temperature at the top, center surface of the component. Air temperature refers to the ambient temperature near the component. Table B-1 Thermally Significant Components Generic Description Max. Allowable Component Temperature (deg.
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Thermal Validation Figure B-1 Thermally Significant Components–Primary Side J42 J8 J7 U17 J29 PCI MEZZANINE CARD J21 J22 J23 J24 U19 U16 P1 U27 U25 U23 U22 U11 U15 J11 J12 U10 U14 PCI MEZZANINE CARD U9 U21 U30 U18 J3 PMC IPMC U8 U13 J30 U20 U7 U6 J13 J14 LAN 1 10/100/1000 10/100/1000 U5 J9 U4 LAN 2 J93 U3 U32 U12 P2 DEBUG J19 U1 ABT/RST J4 4248 0504 MVME6100 Single Board Computer Installation and Use (6806800D58E) 109
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Thermal Validation Figure B-2 B.3 Thermally Significant Components–Secondary Side Component Temperature Measurement The following sections outline general temperature measurement methods. For the specific types of measurements required for thermal evaluation of this board, see Table B-1. B.3.1 Preparation We recommend 40 AWG (American wire gauge) thermocouples for all thermal measurements. Larger gauge thermocouples can wick heat away from the components and disturb air flowing past the board.
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Thermal Validation Allow the board to reach thermal equilibrium before taking measurements. Most circuit boards will reach thermal equilibrium within 30 minutes. After the warm up period, monitor a small number of components over time to assure that equilibrium has been reached. B.3.2 Measuring Junction Temperature Some components have an on-chip thermal measuring device such as a thermal diode.
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Thermal Validation Machining a heatsink base reduces the contact area between the heatsink and the electrical component. You can partially compensate for this effect by filling the machined areas with thermal grease. The grease should not contact the thermocouple junction.
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Thermal Validation B.3.4 Measuring Local Air Temperature Measure local component ambient temperature by placing the thermocouple downstream of the component. This method is conservative since it includes heating of the air by the component. The following figure illustrates one method of mounting the thermocouple.
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Thermal Validation 114 MVME6100 Single Board Computer Installation and Use (6806800D58E)
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Index A F abort/reset switch 29 air temperature range 101 alternate boot images 55 ambient temperature, measuring 113 ambient temperatures 108 applying power 29 features, hardware 59 feedback 14 firmware command utility 41 firmware scan 56 firmware startup sequence 57 firmware, safe start 55 Flash memory 68 B block diagram 61 board component temperatures 107 connectors 27 description 15 dimensions 101 installation 27 board fail LED 29 boundary scan header (J18) 71 C command line rules MOTLoad 40 comme
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Index Flash 68 system 69 MOTLoad command characteristics 38 command line help 40 command line rules 40 command types 31 command versus test 31 described 31 how employed 31 interface 38 list of commands 33 memory requirements 31 prompt explained 38 requirements 31 test suites 33 tests described 32 MPC7457 processor 61 O S settings, VME 41 specifications 101 startup overview 17 switch, abort/reset 29 system controller 62 CPU bus interface 63 I2C serial interface/devices 66 interrupt controller 67 memory co
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HOW TO REACH LITERATURE AND TECHNICAL SUPPORT: Tempe, Arizona, USA 1 800 759 1107 1 602 438 5720 Munich, Germany +49 89 9608 0 For literature, training, and technical assistance and support programs, visit www.emersonnetworkpowerembeddedcomputing.com Emerson Network Power. The global leader in enabling Business-Critical Continuity™ AC Power Systems Connectivity DC Power Systems Embedded Computing Embedded Power Integrated Cabinet Solutions www.emersonnetworkpowerembeddedcomputing.