Technical data

4 Programming Model
PMCspan PMC Carrier Module Installation and Use (6806800A59B)
25
PMC Clock, Request, Grant Assignment
The PCI6150 bridge chip provide individual clock sources and arbitration logic for each PMC
module on the secondary PCI bus. The PMCspan routes the secondary PCI bus Clock,
Request and Grant signals between the PCI6150 bridge chip and the PMC slots as shown in
Tabl e 4 -5.
PMC Present Signal Assignment
The PMCspan hardwires the BUSMODE(4:2)# encoding signals to 001 (binary) for each PMC
slot indicating that the PMCspan supports PCI protocol. The signal BUSMODE1# returned from
each PMC module indicates there is a PMC module installed in the slot and that the PMC
module supports PCI protocol. The PMC Present signals from each PMC slot may be read at
any time following a reset on the PCI6150 GPIO pins. Table 4-6 shows the assignment of the
PMC Present signals to the GPIO pins. Figure 4-7 shows the values in the Serial Clock Mask
register following a reset. Serial Clock Mask bit 13 is 0 in order to enable s_clk_o(9) for the 6150
s_clk input.
Table 4-5. PMC Clock, Request, Grant Assignments
PMC 6150
Clock Source
6150
Request
6150
Grant
1 (Slot 1 on PMCspan16E-002) s_clk_o(0) s_req_l(0) s_gnt_l(0)
2 (Slot 2 on PMCspan16E-002) s_clk_o(1) s_req_l(1) s_gnt_l(1)
3 (Slot 1 on PMCspan26E-010) s_clk_o(2) s_req_l(2) s_gnt_l(2)
4 (Slot 2 on PMCspan26E-010) s_clk_o(3) s_req_l(3) s_gnt_l(3)
Table 4-6. PMC Present to GPIO Assignments
PMC Present Signal GPIO bit
1 (Slot 1 on PMCspan16E-002)
0
2 (Slot 2 on PMCspan16E-002)
1
3 (Slot 1 on PMCspan26E-010)
2
4 (Slot 2 on PMCspan26E-010)
3
Table 4-7. Serial Clock Mask
1514131211109876543210
0001111100000000