Technical data

PMCspan PMC Carrier Module Installation and Use (6806800A59B)
4 Programming Model
20
10h-17h Reserved No No
18h Secondary
Latency Timer
Subordinate
Bus Number
Secondary Bus
Number
Primary Bus
Number
Yes No
1Ch Secondary Status I/O Limit I/O Base Yes No
20h Memory Limit Memory Base Yes No
24h Prefetchable Memory Limit Prefetchable Memory Base Yes No
28h Prefetchable Memory Base Upper 32 Bits Yes No
2Ch Prefetchable Memory Limit Upper 32 Bits Yes No
30h I/O Limit Upper 16 Bits I/O Base Upper 16 Bits Yes No
34h
Reserved
New Capability
Pointer (DCh if
Power
Management
Support;
otherwise,
E4h)
No No
38h Reserved No No
3Ch Bridge Control Interrupt Pin Reserved Yes No
40h Arbiter Control Diagnostic
Control
Chip Control Yes No
44h Miscellaneous Options Timeout
Control
Primary Flow-
through Control
Yes Yes
48h Secondary
Incremental
Prefetch Count
Primary
Incremental
Prefetch Count
Secondary
Prefectch
LineCount
Primary
Prefetch Line
Count
Yes Yes
4Ch Reserved Secondary
Flow-through
Control
Secondary
Maximum
Prefectch
Count
Primary
Maximum
Prefetch Count
Yes Yes
50h Reserved Test Internal Arbiter Control Yes No
Table 4-1. PLX PCI6150 PCI Configuration Register Address Mapping
PCI
Configuration
Register
Address
PC
Writable
Serial
EEPROM
Writable
31 24 23 16 15 8 70
Notes: *Writable only when the Read-Only Register’s Write Enable bit is set
(RRC[7]=1;PCI:9Ch).
Writes to Reserved locations have no effect.
Reads of Reserved locations return zeros.
To ensure software compatibility with other versions of the PCI 6150 family and to ensure
future compantibility, write zeros to all unused bits..
Refer to the individual register descriptions to determine which bits are writable.