Technical data

4
PMCspan PMC Carrier Module Installation and Use (6806800A59B)
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4 Programming Model
Introduction
This chapter describes the programming model for the PMCspan.
PLX PCI6150 Configuration Registers
The PCI Configuration Registers for the PLX PCI6150 PCI-to-PCI Bridge chip are shown in
Tabl e 4 -1. For a detailed register bit description, refer to the PLX PC16150 data book listed in
Appendix A, Related Documentation.
Configuration Transactions
PCI configuration transactions are used to initialize the PCI system including the PCI-to-PCI
bridge and devices on the PMC module. All PCI6150 registers are accessible only in the
configuration space. In addition to accepting configuration transactions for initialization of its
own configuration registers, the PCI6150 also forwards configuration transactions bound for
devices on the PMC module, as well as special cycle generation on the secondary PCI bus.
These two types of configuration transactions are supported by Type 0 and Type 1 configuration
cycles.
Table 4-1. PLX PCI6150 PCI Configuration Register Address Mapping
PCI
Configuration
Register
Address
PC
Writable
Serial
EEPROM
Writable
31 24 23 16 15 8 70
00h Device ID (3388h) Vendor ID* Yes Yes
04h Primary Status Command Yes No
08h Class Code* Revision ID Yes Yes
0Ch
Built-in Self
Test*
Header Type* Primary
Latency Timer
Cache Line
Size
Yes Yes
Notes: *Writable only when the Read-Only Register’s Write Enable bit is set
(RRC[7]=1;PCI:9Ch).
Writes to Reserved locations have no effect.
Reads of Reserved locations return zeros.
To ensure software compatibility with other versions of the PCI 6150 family and to ensure
future compantibility, write zeros to all unused bits..
Refer to the individual register descriptions to determine which bits are writable.