Technical data

3 Functional Description
PMCspan PMC Carrier Module Installation and Use (6806800A59B)
17
Tabl e 3 -2 shows the ECC memory access latency for PMCspan-initiated cycles.
Table 3-2. PMCspan PMC to ECC Memory Access Timing
Access Type PCI Clock Periods Required for:
1st Beat 2nd Beat 3rd Beat nth Beat
32-bit Burst Reads
17 1 1 1
32-bit Burst Writes
31 11
1-Beat Read
17 - - -
1-Beat Write
3- - -
Notes
1. The latency assumes two system clocks for 60X system
bus arbitration.
2. The latency is based on 60ns, fast-page DRAM timing. It
is also assumed that L2 is either disabled or missed.
3. Write timings assume write posting FIFO is initially empty.